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Starvation-Free Handling Cycles During Delay Transactions from Multiple PCI Masters

IP.com Disclosure Number: IPCOM000132466D
Publication Date: 2005-Dec-17
Document File: 2 page(s) / 37K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method within a Peripheral Component Interconnect-to-Peripheral Component Interconnect bridge to enable starvation-free handling cycles as delayed transactions (DT) from multiple PCI masters. Benefits include a cost effective design.

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Starvation-Free Handling Cycles During Delay Transactions from Multiple PCI Masters

Disclosed is a method within a Peripheral Component Interconnect-to-Peripheral Component Interconnect bridge to enable starvation-free handling cycles as delayed transactions (DT) from multiple PCI masters. Benefits include a cost effective design.

Background

Prolonged starvation can cause PCI devices to malfunction, or to be unintentionally dropped.

General Description

The disclosed method contains the following three elements:

§         A cost effective design that uses two machines to provide fair treatment and starvation-free servicing for multiple PCI masters.

§         A pending queue (i.e. pendingQ) FIFO storage. This queue stores only attributes of the cycles that are not able to be serviced immediately.

§         A hardware queuing algorithm that ensures starvation-free servicing to all masters.

When the bridge receives a cycle and decides it should be handled as a DT, the cycle is queued directly (if the DT machine is available). When both DT machines are full, subsequent DT cycles are queued in the pendingQ. At this point, cycles are queued without knowledge of the initiating PCI master.

Whenever a pendingQ entry is occupied, the hardware queuing algorithm begins. The logic only queues masters that do not have prior cycles queued in the DT machines or pendingQ. For masters that have cycles queued, the current cycle is immediately retried on the PCI bus and ignored. This provides room for masters that h...