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Using Two Chip Selects to Enable Quad Rank

IP.com Disclosure Number: IPCOM000132468D
Publication Date: 2005-Dec-17
Document File: 1 page(s) / 30K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method that enables a quad rank DIMM to have two chip selects coming from the host (memory controller), or Advanced Memory Buffer (AMB). Benefits include eliminating the need for two additional signal assignments on the connector pin.

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Using Two Chip Selects to Enable Quad Rank

Disclosed is a method that enables a quad rank DIMM to have two chip selects coming from the host (memory controller), or Advanced Memory Buffer (AMB). Benefits include eliminating the need for two additional signal assignments on the connector pin.

Background

Current applications require four chip selects to be driven from the memory controller or AMB.

General Description

The disclosed method enables a quad rank DIMM to have two chip selects coming from the host or AMB (see Figure 1). The disclosed method uses mux logic integrated into a register/AMB, or an external component that uses the same number of chip selects coming from the DIMM connector and routes out four chip selects on the DIMM. The four chip selects generated on the DIMM choose one of the four ranks on the DIMM.

Advantages

The disclosed method eliminates the need for four chip selects, and can be implemented without changes to the current system. This eliminates the need for having two additional signal assignments on the connector pin, leaving it open for future use.

Fig. 1

Disclosed anonymously