Browse Prior Art Database

Watch-Dog Logic Mechanism in Memory Controllers for Collateral Memory Access Monitoring and Control

IP.com Disclosure Number: IPCOM000132624D
Publication Date: 2005-Dec-27
Document File: 6 page(s) / 30K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a mechanism for implementing a watch-dog logic (WDL) in memory controllers for collateral memory access monitoring and control. Benefits include improved functionality and improved performance.

This text was extracted from a Microsoft Word document.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 27% of the total text.

Watch-Dog Logic Mechanism in Memory Controllers for Collateral Memory Access Monitoring and Control

Disclosed is a mechanism for implementing a watch-dog logic (WDL) in memory controllers for collateral memory access monitoring and control. Benefits include improved functionality and improved performance.

Background

              Conventionally, many mission-critical systems use a real-time operating system (RTOS) with flat address space. Not all RTOSs handle memory protection. As a result, tasks can corrupt the resources of another task. For example, exceeding an array boundary could corrupt the context of another task and thus can hang the system.

      To overcome this, various memory protection mechanisms are available these days. One solution is the guarded memory unit (GMU) within a CPU to control access to specific regions in random access memory (RAM). GMU enables the user to program access permissions for different regions of the system memory using registers. The granularity of the memory protection differs with the various implementations and techniques. When access is granted to a protected region of system memory, the CPU validates the memory access request. For example, certain regions in the system memory can be accessed only when the processor is running in privileged mode. Operating system resources in memory can be protected using GMU, so that applications running in the user context do not have access to these regions. However, GMU is limited in scope. Additionally, GMU consumes CPU resources and cycles.

      Alternatively, in the mechanism discussed in this document, access control, memory monitoring & memory protection is provided by the memory controller itself.

General description

              The disclosed method is a hardware watch-dog mechanism in memory controllers to monitor and control system memory access without expending additional CPU cycles. The method provides a memory access management functionality that is faster and more flexible, feature-rich, and programmable than conventional memory protection mechanisms.

      The disclosed method releases the CPU from providing protection and implements WDL in a memory controller for collateral memory access monitoring and control. The memory controller is located between the CPU and system memory.

      The key elements of the disclosed method include:

•             Watch-Dog Logic (WDL)

•             WDL Control Block (WCB)

•             WDL Cache

•             WDL Control Pins

•             WDL Drivers

Advantages

              The disclosed method provides advantages, including:
•             Improved functionality due to providing watch-dog logic for memory controllers

•             Improved functionality due to providing a wide range of additional memory monitoring and profiling services

•             Improved functionality due to centralizing memory protection for multiple core and multiprocessor environments

•             Improved performance due to reduci...