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Method for dynamic burst length for DDR memory

IP.com Disclosure Number: IPCOM000132625D
Publication Date: 2005-Dec-27
Document File: 3 page(s) / 14K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a dynamic burst length for double data rate (DDR) memory. Benefits include improved functionality and improved performance.

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Method for dynamic burst length for DDR memory

Disclosed is a method for a dynamic burst length for double data rate (DDR) memory. Benefits include improved functionality and improved performance.

Background

              Low-power double data rate synchronous dynamic random access memory is standardized by “Low Power Double Data Rate (LPDDR) SDRAM Specification”, PRN05-DR36 which was published in preliminary form by Joint Electronic Devices Engineering Council (JEDEC) December 2005.

              Conventionally, a synchronous dynamic random access memory (SDRAM) read-burst length is static and can be truncated by a burst terminate command. The write-burst length is static and can be truncated by a precharge command. The storage row address is specified by the memory controller during a first time‑phase. During the second time‑phase, the controller specifies the column address. The number of rows per bank determines the width (number of bits) of the row address. The size of the row determines the width of the column address. The standard specifies the sizes and widths for various densities and configurations of SDRAM memories. They typically have a column address that is less wide (has fewer bits) than the row address. As a result, some bus lines are underutilized during read and write commands.


              In a typical SDRAM bus implementation, a bit-field in a mode register configures the memory to use a fixed burst length for both read bursts and write bursts (typically, 4 or 8 words). Read bursts can be truncated efficiently with a burst terminate command which adds congestion to the command bus. Write bursts can be truncated only by closing the row with a precharge command which can increase subsequent read/write latencies.
              In multiprocessor systems, where different cores execute different types of software algorithms, data traffic on a bus can have different characteristic patterns. Graphics data are served best by short burst lengths. Instruction cache line fills are served best by long burst lengths. However, memory with a single chip select from a single memory controller can be configured for only one burst length at a time regardless of the purpose of the traffic. Reconfiguration of the burst length is a slow process of mode register set commands.

General description

              The disclosed method is dynamic burst length for DDR memory. The method uses

memory-input and controller-output pins during read and write commands. The method provides a temporary burst length pertinent only to the burst that is being invoked by the command. Each individual read and write command must specify its own dynamic burst length.

Advantages

              The disclosed method provides advantages, including:
•             Improved functionality due to providing a dynamic (changeable) burst length for individual memory read and write...