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CAM Team#3: Method of minimizing on-chip CAM noise / power by adaptive slew rate control using BIST

IP.com Disclosure Number: IPCOM000132627D
Original Publication Date: 2005-Dec-28
Included in the Prior Art Database: 2005-Dec-28
Document File: 4 page(s) / 79K

Publishing Venue

IBM

Abstract

Semiconductors memories are designed to meet design specifications even at worst process, voltage, and temperature corners. This implies that if the chip lands in a fast process corner, its design performance will far exceed the design specifications, unnecessarily operating at higher speed then required. This higher performance is great for meeting timing, but the fast transients associated with the fast process corners also create the largest power-supply noise. This noise has been known to cause failures in semiconductor memories and/or the surrounding circuitry. Furthermore, this noise is only aggravated by scaling geometry in which increased current density causes larger IR drop and fast transients produce progressively larger Ldi/dt induced power supply voltage compression.

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CAM Team#3: Method of minimizing on-chip CAM noise / power by adaptive slew rate control using BIST

Switching of highly capacitive memory array lines is the main cause of on-chip power supply noise in semiconductor memories. This degradation of the power supply voltage is especially serious at fast-process corners, which cause fast transients, in turn, creating large Ldi/dt power supply noise. So, a chip at the fast-process corner will generate more noise and cause larger oscillations on the supply voltage than a chip at the nominal or slow-process corner. On the other hand, since chips have to be timed for slow-process, these fast-process chips do not give any speed advantage. This disclosure describes an adaptive method for progressively reducing unnecessary on-chip noise while maintaining specified macro speed. Although described in the context of Content Addressable Memory (CAM) this disclosure can extended to any driver with high capacitance load.

Fig. 1 shows a simplified architecture of a CAM. For the search operation, the CAM uses Search-lines (SL) and Match-lines (ML). The search data on the SLs is compared with the contents of every entry, and the search results of each word develop in parallel on their corresponding MLs.

Search D ata

Search D ata

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1 0 1 0

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Search-Lines

(SLs )

Search-Lines

(SLs )

Figure 1: General CAM Architecture

Since all entries are activated during a search operation, CAMs consume a lot of power and draw a large current from the supply. ML and SL switching are biggest contributors to the CAM power and noise. To reduce CAM noise the instantaneous current-draw associated with the charge-up of these highly capacitive lines needs to be spread over a larger time period.

Fig. 2 shows a circuit that can be used to control the drive strength of the search-line drivers. The header and footer devices provide a path to VDD and GND and act as current limiting devices. These devices can be shared amongst multiple drivers thereby minimizing the area overhead. Fig.2 shows a three bit (SEL2:0) control of the header and footer devices allowing eight combinations of drive strengths for the search-line drivers. A larger number of control bits can provide more granularity. The Header/Footer select bits are controlled by the BIST controller. The BIST controller tests the CAM

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at-speed for different settings of the header/footer select bits and finds the lowest strength setting that still meets design specified timing.

Figure 2: Modified search-line driver for reduced noise

The scheme of Fig. 2 could also be used to reduce the strength of the field output drivers. In fact, that scheme can be used to reduce...