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Calculating Noise Rejection Curve for ASIC PLLs Using Sensitivity Function

IP.com Disclosure Number: IPCOM000132630D
Original Publication Date: 2005-Dec-28
Included in the Prior Art Database: 2005-Dec-28
Document File: 9 page(s) / 838K

Publishing Venue

IBM

Abstract

Mixed signal design such as ASIC includes decoupling capacitors in various locations of design to minimize effect of noise in circuit performance. However, adding these decoupling capacitors do impact the global resonance in addition to local resonance. In todays design environment that many clock frequency domains exist in the design, it is important to know the resonance frequency in order to minimize or control many unwanted circuit behavior such as jitter due to oscillation of power supply. In a ASIC design also may exist various harmonics that are "by products" of switching events and they also as well can coincide with local and global resonance. Identifying these resonance point(s) is a key to identifying the noise source in the design.

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Calculating Noise Rejection Curve for ASIC PLLs Using Sensitivity Function

Main Idea

The method shown in this disclosure calculates and estimates the resonance using "PCB Inductance", " Near and Far Package Vdd & Gnd parasitic", "on Module Capacitors", "IO Capacitors", "on Chip Capacitors" and total "Chip Capacitance" .

Mixed signal design such as ASIC includes decoupling capacitors in various locations of design to minimize effect of noise on circuit performance. However, adding these decoupling capacitors impact the global resonance in addition to local resonance. In today's design environment where many clock frequency domains exist in the design, it is important to know the resonance frequency in order to minimize or control many unwanted circuit behavior such as jitter due to oscillation of power supply. In an ASIC design there also may exist various frequency harmonics that are "by products" of switching events and they also can coincide with local and global resonance. Identifying these resonance point(s) is a key to identifying the noise source in the design.

The method described here can map "PCB Inductance", package near and far parasitic RLC with a circuit representation of a package decoupling capacitor, IO decoupling capacitor, on chip decoupling capacitor and chip RC to calculate the resonance and plot " Impendence vs Frequency" for the range of operation. In addition, the topology can be adapted to user specific requirements and model different circuit configurations such as eliminating IO Decaps if not needed, or including a much more complex package or chip model in the simulation. Since the simulation runs quickly due to the simplified model, the benefit and trade-offs of adding decoupling schemes can be analyzed and resonance frequency can be calculated until an optimal solution that will lead to better noise minimization and power distribution system is obtained. In addition, this circuit topology is not IP protected so customers can perform simulation or diagnostic analysis themselves.

One way to reduce the resonance peaks is by lowering the Q of the circuit. This can be done practically by inserting a resistance in series with one of the capacitors. Our circuit topology shows the benefit and trade-offs of this approach from "Chip" side or "Package" side. Note that both locations reduce the peak of the resonance, but the off-resonance effects are quite different. Resistance in the "Chip " tends to increase the impedance at all frequencies above the resonance, while the resistance in the "Package" increases impedance below the resonant frequency.

Diagram below shows the circuit that will plot the "Impendence vs Frequency". Note that any of the circuit values can be changed on the fly by clicking on the elements and also any of the branch can be eliminated or modified as user requires.

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Plot below shows "Impendence vs Frequency" and "Phase vs Frequency"

Numbers below summarize the values used in an...