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Reducing Die Level Stress in Stacked Packages

IP.com Disclosure Number: IPCOM000132637D
Publication Date: 2005-Dec-28
Document File: 2 page(s) / 15K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method that reduces die level stresses in stacked packages by extending the die attach film over all of the active circuitry on the die

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Reducing Die Level Stress in Stacked Packages

Disclosed is a method that reduces die level stresses in stacked packages by extending the die attach film over all of the active circuitry on the die.

Background

There is a need to reduce the stresses in stacked packages that are directly related to electrical performance (i.e. Gm shift). Currently, the spacer is extended along the direction of the array cells; however, this does not solve the problem for newer architectures which require that the stresses be uniform over the entire die.

Figures 1 and 2 show the current method of stacking two flash die of the same size using a silicon spacer. In Figure 1, the die attach film does not extend to the edge of the die to account for inaccuracies from the pick and place. The spacer is typically extended along the array cell direction. However, due to the presence of the wire bond, the spacer along that direction is always smaller than the bottom die (see Figure 2). The CTE of the die, the mold compound, and the die attach material are typically in the order of 3, 10, and 100 respectively. This CTE mismatch leads to very high stresses near the triple point A. Transistor performance, such as Gm shift and Vt shift, have been shown to be a function of stress. Maintaining a uniform and low stress is a key requirement for good flash die operation.

General Description

The disclosed method extends the die attach film (i.e. the film on top of the bottom flash die) to the edge of the bottom die...