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Efficient Power Reduction in the Design of Digital Signal Processing Modules

IP.com Disclosure Number: IPCOM000143872D
Published in the IP.com Journal: Volume 6 Issue 12B (2007-01-10)
Included in the Prior Art Database: 2007-Jan-10
Document File: 2 page(s) / 28K

Publishing Venue

Siemens

Related People

Juergen Carstens: CONTACT

Abstract

Radio receivers have to cope with signals at a wide range of input power levels (typically 70 to 80 dB at the antenna). In high speed, high data-rate signal processing systems, the number representation is fix-point equivalent to integers with a hard-coded exponent. Signal processing modules have to cope with this high magnitude changes by a sufficiently high dynamic range or a sophisticated leveling control system. Due to this problem the signal processing modules require a costly design in terms of complexity and thus IC area and power consumption, which reduces the system performance. In most of the practical use cases, the provided dynamic range is not used. Especially in a typical medium low power level (in absence of interferers) a considerable amount of the digital dynamic range is unused. Due to two's complement number representation all unused high bits are toggling with every sign change. This power drain increases with lower signal levels. Especially in mobile applications it is of high interest to provide a strategy to avoid unnecessary switching activity in case of low power signals and thus to reduce the power consumption effectively.

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Efficient Power Reduction in the Design of Digital Signal Processing Modules

Idea: Gernot Hueber, AT-Linz

Radio receivers have to cope with signals at a wide range of input power levels (typically 70 to 80 dB at the antenna). In high speed, high data-rate signal processing systems, the number representation is fix-point equivalent to integers with a hard-coded exponent. Signal processing modules have to cope with this high magnitude changes by a sufficiently high dynamic range or a sophisticated leveling control system. Due to this problem the signal processing modules require a costly design in terms of complexity and thus IC area and power consumption, which reduces the system performance. In most of the practical use cases, the provided dynamic range is not used. Especially in a typical medium low power level (in absence of interferers) a considerable amount of the digital dynamic range is unused. Due to two's complement number representation all unused high bits are toggling with every sign change. This power drain increases with lower signal levels. Especially in mobile applications it is of high interest to provide a strategy to avoid unnecessary switching activity in case of low power signals and thus to reduce the power consumption effectively.

Therefore, an optimized solution is proposed that offers an efficient architecture by several means. The problem of unwanted activity in many sign bits can be overcome by adding an offset to the signal (see Fig. 1 and 2). Thus the signal becomes purely positive (or negative). After typical signal processing tasks, the offset has to be removed again, which can easily be done since the exact value is known. The wanted transfer function H(z) is applied to an input sequence x(k): y(k) = x(k)*H(z).

This approach adds an offset DCin to the input sequence xDC(k)=x(k)+DCin. The filter transfer function H(z) is applied to the transformed input signal sequence xDC(k):

yDC(k) = x(k)*H(z)+DCin*H(z) = x(k)*H(z)+DCinGDC

where GDC is the DC gain of the transfer function H(z). Furthermore, the wanted output sequence y(k) is obtained by removing the DC offset agai...