Browse Prior Art Database

Buffer Device for memory modules (DIMM)

IP.com Disclosure Number: IPCOM000144850D
Original Publication Date: 2007-Feb-10
Included in the Prior Art Database: 2007-Feb-10
Document File: 1 page(s) / 56K

Publishing Venue

Siemens

Related People

Juergen Carstens: CONTACT

Abstract

The demand for both the amount of memory and the speed of the memory bus are increasing. However, adding more DIMMs (Dual In-line Memory Module) to a system increases the electrical loading on the command/address bus (CA) and on the data bus (DQ). A DIMM consists of a defined number of SDRAM (Synchronous Dynamic Random Access Memory) components which share the same CA bus. The DQ bus is a point to point connection or a point to multiple point connection. The high electrical load therefore affects mainly the CA bus. At present, a "Fully Buffered DIMM (FBDIMM)" is used which contains a so called "Advanced Memory Buffer (AMB)" for buffering both the DQ bus and the CA bus so that more SDRAM components can be added on a DIMM. The AMB has a DRAM interface on one side and a high speed link with a dedicated protocol on the other side. The AMBs are connected in a chain. This architecture, however, implies bigger access latencies since the data frame must be forwarded from the first to the next AMB until the desired AMB (module) has been reached. The data from the AMB to the memory controller undergoes the same forwarding procedure as the sent data. Moreover, this architecture has higher power consumption than conventional DIMMs and it requires a completely new architecture of the memory bus, new memory controllers and mother board designs.

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Buffer Device for memory modules (DIMM)

Idea: Maurizio Skerlj, DE-Muenchen; Christian Mueller, DE-Muenchen

The demand for both the amount of memory and the speed of the memory bus are increasing. However, adding more DIMMs (Dual In-line Memory Module) to a system increases the electrical loading on the command/address bus (CA) and on the data bus (DQ). A DIMM consists of a defined number of SDRAM (Synchronous Dynamic Random Access Memory) components which share the same CA bus. The DQ bus is a point to point connection or a point to multiple point connection. The high electrical load therefore affects mainly the CA bus.

At present, a "Fully Buffered DIMM (FBDIMM)" is used which contains a so called "Advanced Memory Buffer (AMB)" for buffering both the DQ bus and the CA bus so that more SDRAM components can be added on a DIMM. The AMB has a DRAM interface on one side and a high speed link with a dedicated protocol on the other side. The AMBs are connected in a chain. This architecture, however, implies bigger access latencies since the data frame must be forwarded from the first to the next AMB until the desired AMB (module) has been reached. The data from the AMB to the memory controller undergoes the same forwarding procedure as the sent data. Moreover, this architecture has higher power consumption than conventional DIMMs and it requires a completely new architecture of the memory bus, new memory controllers and mother boa...