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PLL With Adaptive Bandwidth for Jitter Optimization

IP.com Disclosure Number: IPCOM000145668D
Publication Date: 2007-Jan-22
Document File: 5 page(s) / 267K

Publishing Venue

The IP.com Prior Art Database

Abstract

A conventional phase-locked loop (PLL) using a phase and frequency detector (PFD) has a low-pass transfer function for input reference jitter while a high-pass transfer function for VCO jitter. It is desirable to have the loop bandwidth being automatically adjusted according to the reference jitter amplitude. This invention proposes an adaptive bandwidth PLL which takes advantage of a bang-bang phase detector (BBPD). The BBPD-based PLL has a nonlinear characteristic (due to slew-limiting) that its loop bandwidth is inversely proportional to the input reference jitter amplitude. Therefore, for jittery reference clock, the bandwidth can be automatically adjusted to reduce the amount of reference jitter being passed through to the output.

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INVENTION DISCLOSURE FORM

1.   Title of the invention:

PLL With Adaptive Bandwidth for Jitter Optimization

3.      Summarize the invention in the following provided space:

A conventional phase-locked loop (PLL) using a phase and frequency detector (PFD) has a low-pass transfer function for input reference jitter while a high-pass transfer function for VCO jitter. It is desirable to have the loop bandwidth being automatically adjusted according to the reference jitter amplitude. This invention proposes an adaptive bandwidth PLL which takes advantage of a bang-bang phase detector (BBPD). The BBPD-based PLL has a nonlinear characteristic (due to slew-limiting) that its loop bandwidth is inversely proportional to the input reference jitter amplitude. Therefore, for jittery reference clock, the bandwidth can be automatically adjusted to reduce the amount of reference jitter being passed through to the output.               

4.      Summarize what has been done before in the following provided space:

For a conventional PLL using a PFD, the input reference clock has a low-pass transfer function while the VCO jitter has a high-pass transfer function. Depending on how clean the reference clock is (i.e., the amount of the reference clock jitter), the loop bandwidth has to be manually adjusted to find out the optimum bandwidth which gives the minimum jitter.       

5.      Describe the problem(s) you are trying to solve in the following provided space:

The manual adjustment of the PLL bandwidth is time-consuming and causes a lot of inconvenience for customers. This invention proposes a nonlinear PLL whose bandwidth is automatically adjusted to minimize input jitter.     

6.      Summarize the advantage(s) and/or value(s) in the following provided space:

The proposed adaptive bandwidth PLL simplifies the optimum bandwidth selection for input jitter minimization.

8.   List or attach any prior art of which you are aware.  Prior art may include publications, data books, application notes, products, and patents and patent applications:

M. Mansuri, Chih-Kong Ken, “Jitter optimization based on phase-locked loop design parameters,” IEEE Journal of Solid-State Circuits, vol. 37, pp. 1375 – 1382, Nov. 2002.

R.C. Walker, “Designing bang-bang PLLs for clock and data recovery in serial data transmission systems,” in Phase-Locking in High-Performance Systems, B. Razavi, Ed: Wiley-IEEE Press, 2003.

Patent Description...