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Distributed Dataline Pull Down To Increase Write Margin

IP.com Disclosure Number: IPCOM000145670D
Publication Date: 2007-Jan-22
Document File: 6 page(s) / 858K

Publishing Venue

The IP.com Prior Art Database

Abstract

Dataline pull downs are distributed across the dataline to reduce the highest dataline voltage the CRAM cell sees. By adding simple additional pull downs, the voltage drop across the dataline can be dramatically reduced and improve the write margin of the CRAM cell.

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Distributed Dataline Pull Down To Increase Write Margin

Invention

Dataline pull downs are distributed across the dataline to reduce the highest dataline voltage the CRAM cell sees. By adding simple additional pull downs, the voltage drop across the dataline can be dramatically reduced and improve the write margin of the CRAM cell.

 

Background

CRAM cells are used in FPGA to configure the logic, look-up tables, and routing. Before the FPGA can be used, a program for the desired logic function must be loaded. This loading process “programs” certain CRAM patterns to achieve the desired function. These CRAM cells are arranged in such a way that the “datalines” of the cells are connected in the “X” direction and the “Address lines” are connected in the “Y” direction, as shown in figure 1. A large array of CRAM cells can have a long dataline. A long dataline can have a high resistance; during “programming”, the driver of the dataline drives through the high resistance of the dataline. When programming the CRAM cell, the current going from the CRAM to the driver through the dataline can have a significant voltage difference at the dataline between the driver and the CRAM cell. This will reduce the “write margin”. “Write margin” is defined as the voltage available on the “Address line” minus the voltage required to on the “Address Line” to “program” the CRAM cell, as shown in figure 2. To ensure programming of all CRAM cells, the write margin needs t...