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Early LOD Process for Solid-State Image Sensors

IP.com Disclosure Number: IPCOM000145684D
Publication Date: 2007-Jan-22
Document File: 2 page(s) / 39K

Publishing Venue

The IP.com Prior Art Database

Abstract

A process to fabricate an LOD antiblooming structure prior to the field oxide for full frame type image sensor has been described above. In summary, it starts with growing a silicon dioxide layer on top of a silicon substrate; depositing a silicon nitride layer on top; depositing a first layer of photoresist and forming an opening; etching an opening in the silicon nitride layer to form the to-be field oxide region and implanting P+ to form the channel stop; removing the first layer of photoresist; depositing a second layer of photoresist and forming an opening and implanting N+ to form the LOD; removing the second layer of photoresist; oxidizing the substrate to form the field oxide; and eventually the rest of the standard CCD process steps will then be carried out.

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Early LOD Process for Solid-State Image Sensors

Current Lateral Overflow Drain (LOD) for antiblooming on full-frame type image sensors are formed self-aligned to the edge of the thick field oxide (FOX) underneath the CCD gate electrodes. Since high energy ion-implantation is used to form the LOD, and each ion at a specific energy yields a certain penetration known as projected range, the slightly thicker edge portion of the FOX known as the “bird’s beak” prevents the ions from forming the LOD properly adjacent to the FOX.

The effectiveness or the conductivity of the LOD is proportional to its cross-sectional dimension. One of the options of improving antiblooming without increasing the LOD drawn dimension is to ensure that the LOD is formed prior to the FOX formation. The purpose of this disclosure is to introduce a process such that the LOD can be processed in such a way.

Silicon nitride

 
                                                                                                                       

Nitrde

 

                                                                                                                                                                       Silicon dioxide     p-epi

 

                                                                                                                                               

*Grow a gate dielectric and deposit a silicon nitride layer.

 

                                                                                                                Figure 1

                                                                                   

           
 

Resist #1

 
     
 
 
     
 

*Define the Channel Stop opening by using resist

mask #1.

Silicon nitride

 
*Etch silicon nitride.

Nitrde

 
*Implant Channel Stop.

                                                                                    Figure 2

                                                                                                                                               

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