Browse Prior Art Database

Method for a silicon-copper IHS and direct silicon-to-silicon bonding

IP.com Disclosure Number: IPCOM000145865D
Publication Date: 2007-Jan-30
Document File: 4 page(s) / 28K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a silicon-copper hybrid integrated heatsink (IHS) and direct silicon-to-silicon bonding. Benefits include improved thermal performance, improved reliability, and improved cost effectiveness.

This text was extracted from a Microsoft Word document.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 51% of the total text.

Method for a silicon-copper IHS and direct silicon-to-silicon bonding

Disclosed is a method for a silicon-copper hybrid integrated heatsink (IHS) and direct silicon-to-silicon bonding. Benefits include improved thermal performance, improved reliability, and improved cost effectiveness.

Background

      As circuit densities and power levels of microprocessors increase, thermal management becomes increasingly critical. Heat spreading and power removal from the silicon die are challenging. Conventional approaches where the die is bonded to a copper heatsink using appropriate solders, such as thermal interface materials (TIMs), no longer suffice (see Figure 1).

      One solution is to thin the die to 50-120 microns following wafer fabrication and attach it to a copper heatsink, using a metallic TIM 5-20 microns thick. This solution provides a better than 30% increase in the thermal design power. However, unwanted stresses are placed on the thinned die due to large differences in the coefficients of thermal expansion (CTE) between the silicon and the copper. Silicon has a CTE of 4. 1 X 10e-6/K and Copper has a CTE of 17 X 10e-6/K. The difference in the CTE is greater than four fold. It causes transistor parameters to be adversely affected and can result in failure of interlevel dielectrics, particularly with low-dielectric constant materials, which currently display poor mechanical properties.

      Dealing with increasing power densities and temperatures for future generation microprocessors requires innovative approaches in packaging. They must relate to addressing thermal issues while mitigating packaging-induced stresses in transistors and reducing packaging costs.

      Another possible solution is thin die, thin TIM (TDTT). The processed wafer is thinned to ~100 microns and bonded to a copper IHS, utilizing an Au-Sn solder 5-20 microns thick. The melting temperature of the Au-Sn TIM material is ~330°C. Cycling the structure between 330°C and room temperature results in the introduction of substantial stresses in the transistors. The biaxial stress values in the transistors have been computed to be about 790 Mpa for a 100 micron die.

General description

      The disclosed method includes a composite IHS with a layer of poly or amorphous silicon deposited on copper heatsinks with an intermediate layer of a silicide-forming metal. The key elements of the disclosed method include:

•     Deposition of Ti (or Ni) on Cu heatsinks followed by a thin film of silicon

•     Heat treatment of the composite, if required, to temperatures <500°C to form a silicide between the copper and the silicon

•     Polishing of the silicon, as required

•     Direct bonding of the die to the silicon surface on the IHS and heating to temperatures of
~250°C to complete the bonding p...