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Method for platform clock noise cancellation using PLL acquisition

IP.com Disclosure Number: IPCOM000146263D
Publication Date: 2007-Feb-08
Document File: 4 page(s) / 75K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for platform clock noise cancellation using phase-locked loop (PLL) acquisition. Benefits include improved functionality and improved performance.

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Method for platform clock noise cancellation using PLL acquisition

Disclosed is a method for platform clock noise cancellation using phase-locked loop (PLL) acquisition. Benefits include improved functionality and improved performance.

Background

      Conventionally, harmonics generated by clock signals in a PC can extend into frequencies well into the GHz region (see Figure 1).

      Clock harmonics are known to cause serious interference to sensitive wireless devices operating in a PC or laptop computer. This is especially true when placed in a small form factor where space is not available for shielding the antenna from digital electronics (see Figure 2).

 

General description

      The disclosed method is platform clock noise cancellation using PLL acquisition. The method reduces the levels of the harmonics that fall into susceptible radio channels. The method applies to square waves with a regular duty cycle or with arbitrary duty cycles.

      The disclosed method cancels the harmonic falling into the radio channel using an auxiliary signal that is identical to the original signal in magnitude but shifted by 180 degrees. The auxiliary signal is obtained using PLL acquisition.

Advantages

      The disclosed method provides advantages, including:
•     Improved functionality due to providing platform clock noise cancellation using PLL acquisition

•     Improved functionality due to providing wireless noise cancellation without requiring heavy shielding
•     Improved performance due to canceling the harmonic falling into the radio channel

Detailed description

      The disclosed method is platform clock noise cancellation using PLL acquisition. For example, a square wave with a duty cycle of 50% contains odd harmonics that fall off as 1/n2. In the case of wireless interference, harmonics of considerably high order (such as beyond 30) can still be problematic. For example, a 100-MHz reference clock contains harmonics of 300, 500, and 700 MHz. The 25th harmonic appears as a tone at 2500 MHz. While harmonics of higher order are present, those beyond 12 to 15 are not typically required to maintain signal integrity. If they can be eliminated from the signal, the operation of the platform is not affected.

      Harmonics a...