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Method for a multiple power level memory cell and low power level register file

IP.com Disclosure Number: IPCOM000146282D
Publication Date: 2007-Feb-09
Document File: 6 page(s) / 147K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a multiple power level memory cell and low power level register file. Benefits include improved functionality, improved performance, improved power performance, improved design flexibility, and improved reliability.

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Method for a multiple power level memory cell and low power level register file

Disclosed is a method for a multiple power level memory cell and low power level register file. Benefits include improved functionality, improved performance, improved power performance, improved design flexibility, and improved reliability.

Background

      As the industry moves to multiple-core platforms, chip power becomes increasingly critical  because circuits on the chip share limited power resources. Additionally, power dissipation and its limitation have a direct impact on the performance of a product.

      Power is conventionally limited by decreasing the level of the power supply to the whole chip. However, this approach is problematic. Critical circuits can lose performance.

State elements and memory circuits can loose their states. Memory circuits cannot be written. For example, the core memory cell is located at the word line (WL). The cell includes two back-to-back inverters and two negative metal oxide semiconductor (NMOS) pass gates. If VCC1 or VCC2 is lower than VCC3, flipping the memory cell for a write operation becomes harder. Writing can become impossible if the difference in the power supply is large. The same condition applies when both VCC1 and VCC2 are lower than VCC3 (see Figure 1).

       Lowering the supply for all other circuits, except memory cells, achieves both leakage and dynamic power reduction. However, memory cells at high supply with input signals (wordline or data) coming from a low-supply domain cannot be written for a wide range of power supplies. If any of the inputs to a memory cell comes from a low-supply domain, the capability to flip the contents of the memory cell becomes compromised. For example, the memory cell cannot be flipped with a supply difference of 267 mV. The range of the difference should be from the CMOS threshold voltage to the nominal supply. The range can reach 700 mV (see Figure 2).

      An alternative solution is to lower the supply to signal staging buffers only, while maintaining state elements, memory cells, and read paths at the higher power level. This technique is a minimalist solution that has a limited impact on supply reduction and power (see Figure 3).

General description

      The disclosed method is a multiple power level memory cell and low power level register file. The method bypasses the voltage range limitations by using multiple supply levels in a chip. State elements, such as memory cells, remain at the high supply level. All other circuitry is at a lower supply level. The high level for memory elements provides the required minimum supply that maintains the memory contents and prevents state loss, especially in the presence of gate defects. The method provides low leakage and dynamic power levels. Additionally, the meth...