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Method for a fast-lock low-jitter delay-locked loop using a dual charge pump and lock control circuit

IP.com Disclosure Number: IPCOM000146285D
Publication Date: 2007-Feb-09
Document File: 4 page(s) / 66K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a fast-lock low-jitter delay-locked loop using a dual charge pump and lock control circuit. Benefits include improved functionality, improved performance, and improved cost effectiveness.

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Method for a fast-lock low-jitter delay-locked loop using a dual charge pump and lock control circuit

Disclosed is a method for a fast-lock low-jitter delay-locked loop using a dual charge pump and lock control circuit. Benefits include improved functionality, improved performance, and improved cost effectiveness.

Background

      Conventionally, phase-locked loops (PLL) and delay-locked loops (DLL) are used for the clock synchronization. The locking time and the jitter performance are important characteristics. DLLs are preferred over PLLs in applications without clock multiplication due to the DLLs’ stability and faster locking time. Because the noise in the voltage-controlled delay line (VCDL) does not accumulate over many clock cycles, DLLs offer better jitter performance than PLLs. The fast locking and low jitter enable a system to reduce the wait time required before it can operate.

      A typical building block of a conventional DLL is comprised of the following:

•     Phase frequency detector (PFD)

•     Charge pump

•     Loop filter

•     VCDL

•     Additional circuitry to overcome the problem of a limited locking range

General description

      The disclosed method is a fast-lock low-jitter delay-locked loop using a dual charge pump and lock control circuit. The method uses two types of loop tuning, the fine-tuning loop and a coarse tuning loop. The coarse-tuning loop is used to reduce the lock time and the fine-tuning loop is used when the DLL is close to lock to reduce the output jitter.

      The disclosed method provides a clock deskewing buffer in microprocessor or memory applications.

      The key elements of the disclosed method include:

•     Sequential PFDs

•     Precharged PFDs

•     Two charge pumps

•     Adjustable pulse width circuit

•     Lock control circuit

Advantages

      The disclosed method provides advantages, including:
•     Improved functionality due to providing a fast-lock low-jitter delay-locked loop using a dual charge pump and lock control circuit

•     Improved functionality due to providing an adjustable tuning point between coarse and fine tuning

•     Improved functionality due to reducing the silicon surface area required
•     Improved performance due to providing fast locking
•     Improved performance due to reducing jitter

•     Improved cost effectiveness due to using a small chip area, reducing the cost of fabrication

Detailed description

      The disclosed method is a fast-lock low-jitter delay-locked loop using a dual charge pump and lock control circuit. The method uses two PFDs and two charge pumps. One PFD is sequential and one is precharged. The system uses an adjustable pulse width circuit to turn off the coarse charge...