Browse Prior Art Database

Method for the fabrication of copper interconnects in low-k dielectrics

IP.com Disclosure Number: IPCOM000146539D
Publication Date: 2007-Feb-16
Document File: 6 page(s) / 324K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for the fabrication of copper interconnects in low dielectric constant (low‑k) dielectrics. Benefits include improved functionality and improved performance.

This text was extracted from a Microsoft Word document.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 38% of the total text.

Method for the fabrication of copper interconnects in low-k dielectrics

Disclosed is a method for the fabrication of copper interconnects in low dielectric constant (low‑k) dielectrics. Benefits include improved functionality and improved performance.

Background

      Chemical-mechanical polishing (CMP) is the conventional solution to removing copper and barrier material from the field area of a wafer. A major concern in the integration of copper (Cu) with low-k dielectrics is the capability of these mechanically weak materials to survive the stress placed on them by CMP technology. Additionally, the barrier becomes thinner as the feature size of on-chip interconnects decreases. Stopping the copper CMP process on the barrier becomes increasingly difficult and results in high dielectric erosion. The conventional CMP process requires relatively high (2 psi) pressure to remove barrier material. As a result, the process causes excessive interlayer dielectric (ILD) loss and creates defects, such as bent lines and scratches.

      Alternative stress-free planarization solutions, such as electropolishing, have been proposed for copper interconnect fabrication. However, the low planarization efficiency of electropolishing can lead to significant over-polishing to overcome within-die copper thickness variations, resulting in copper recesses in lines. Conventionally, no method is available to stop copper dissolution in lines during copper clearing. Performing a CMP step to preplanarize the topography before electropolishing reduces the copper recess but does not solve the problem completely. Additionally, no stress-free barrier removal process is available that does not lead to low-k ILD damage or copper loss.

      Electropolishing stops on an electrically discontinuous barrier.

      The etch rate of carbon-doped oxide (CDO) with a dielectric constant greater than 2.9 varies significantly from the etch rate for CDO with a dielectric constant less than 2.5 in a chemistry containing hydrogen-fluoride (HF).  

      The conventional method can be implemented using the following steps to fabricate copper damascene interconnections:

1.   Deposit and pattern ILD layer 1 to create a trench with a thickness designated as D (see Figure 1).

2.   Deposit barrier and seed material over the trenches/vias etched in ILD layer 1 (see Figure 2).

3.   Electrochemically deposit a copper layer to fill the features (see Figure 3).

4.   Perform CMP to remove the copper from the barrier material on the field regions (see Figure 4).

5.   Perform CMP to remove the barrier from the field region and planarize the copper surface of the damascene features (see Figure 5).

      Performing CMP (especially the barrier polish) results in significant ILD loss (D-D1) and copper line-depth reduction, leading t...