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Method for an OS scheduler for SMT systems based on the number of instructions retired

IP.com Disclosure Number: IPCOM000146800D
Publication Date: 2007-Feb-23
Document File: 6 page(s) / 87K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for an operating system (OS) scheduler for simultaneous multithreading (SMT) systems based on the number of instructions retired. Benefits include improved functionality, improved performance, and improved reliability.

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Method for an OS scheduler for SMT systems based on the number of instructions retired

Disclosed is a method for an operating system (OS) scheduler for simultaneous multithreading (SMT) systems based on the number of instructions retired. Benefits include improved functionality, improved performance, and improved reliability.

Background

      Hyperthreading (HT) is a 32-bit superscalar model with a core speed that is triple the bus speed. HT Technology is an Intel Corporation trademark.

      Conventional commercial SMT implementationshighly utilize the computing horsepower of a central processing unit(CPU). By overlapping the computing requests from different logical CPUs on the same core, the fine-gradedynamic resource sharing boosts the throughput of the CPU. However, this processing undermines the fairness and promptness of the time-sliced OS scheduler because the time slice no longer stands for the amount of resource one process occupies. Instead, a time slice indicates how long a process stays active, such as two (or more) with its siblings. If the time-slice is not replaced as the basis of OS scheduler, a bias always exists for some types of workload. Furthermore, the bias is changeable according to CPU’s arbitration design when resource contention takes place.

      Multithread-enabled OS performance fluctuateswith different workloads. After making the OS scheduler SMT aware, the fairness remains unguaranteed due totimeslicingremaining as an indicator for resource usage. Resource contention exists no matter how sibling processes are combined on the same core. As long as timeslicingremains the resource usage indicator for each process,anSMT CPU always trades throughput for bias/promptness, no matter what arbitration algorithm is used.

      One conventional solution is to combine processes with orthogonal resource usage characters on different logical CPUs in the same core. This approach increases the CPU’s throughput by increasing parallelism. However, this solution doesnot solve fairness and promptness issues introduced by dynamic resource sharing.

      An alternative solution is to modify the CPU’s front end to honor a process/thread’s priority. This solution attempts to solve the problem at the CPU level. Additionally, this solution is expensive.Lengtheningthe CPU front-end’s pipeline decreases the CPU’s throughput by increasing the branch misprediction penalty and harming the promptness of instruction fetch/prefetch’s self-adaptive algorithm.

General description

      The disclosed method is an OS scheduler based on an instruction-retired performance counter. The method avoids any possible biases introduced by the SMT CPU and retains (or even enhances) the fairness ofthe OS scheduler. The disclosed method automatically resolves the issue...