Browse Prior Art Database

Method for multi-threaded decompression in the preboot environment

IP.com Disclosure Number: IPCOM000146803D
Publication Date: 2007-Feb-23
Document File: 5 page(s) / 155K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for multi-threaded decompression in the preboot environment. Benefits include improved functionality and improved performance.

This text was extracted from a Microsoft Word document.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 45% of the total text.

Method for multi-threaded decompression in the preboot environment

Disclosed is a method for multi-threaded decompression in the preboot environment. Benefits include improved functionality and improved performance.

Background

      In personal computer (PC) systems and consumer electronics, flash devices are popular storage media for firmware and other middleware images. Typically, these images are compressed to minimize their size. When deployed on a target machine, the image must be decompressed to the preferred base for execution, such as random access memory. The conversion results in a time delay that hinders system performance.

      The decompression delay varies with the compression algorithm. Increased complexity lengthens the delay. However, complex algorithms, such as prediction by partial match (PPM), are required to achieve a high compression ratio. In a worse case, decompression may take minutes, which is not acceptable to users. As a result, the compression ratio must be balanced with decompression performance to achieve a compromise. Some applications have strict requirements for both compression and performance. For example, firmware requires a fast boot time and a small size.

      Many PC and consumer electronics systems have more than one processor. For example, a PC can have hyper-threading, multiple cores, or multiple processors. A mobile phone may have a base-band digital signal processor (DSP) and an embedded processor for control. In a preboot phase, one processor performs the boot strap flow and all others are idle. This processor is referred to as a boot strap processor (BSP). The other processors are referred to as application processors (APs).

      In the conventional basic input/output system (BIOS), firmware, or operating system (OS) loader, the decompression process is single thread. A single processor must finish all decompression although multiple logical processors exist in the system.

      “Extensible Firmware Interface, update -001”, dated November 2003 was released by Intel Corporation, Inc.

      Hyper-threading technology (HT) is a 32-bit superscalar model with a core speed that is triple the bus speed. HT Technology is an Intel Corporation trademark.

      The LZMA compression algorithm is available as part of the LZMA SDK, release 4.32, dated December 2005 by Igor Pavlov.

General description

      The disclosed method is multi-threaded decompression in the preboot environment. The method uses hyper-threading, multi-core and multi-processor technology to decompress images. The method is generic and independent of specific compression algorithms. This infrastructure applies to the preboot phase with the basic input/output system (BIOS), extensible firmware interface (EFI), and embedded and commercial OS loaders. By using th...