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An Easy Programmable Structure ("EPS") for Chip ID and Version Control

IP.com Disclosure Number: IPCOM000146921D
Original Publication Date: 2007-Feb-27
Included in the Prior Art Database: 2007-Feb-27
Document File: 5 page(s) / 84K

Publishing Venue

IBM

Abstract

This article describes an Easy Programmable Structure ("EPS"), which can be used for chip ID and version control. The EPS is a physical structure implementable at chip level. Since it allows easy changes in any level of metal, the benefits and its attendant cost saving are considerable.

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An Easy Programmable Structure ("EPS") for Chip ID and Version Control

A chip design evolves over time for various reasons, such as to correct errors or to add functionality. To keep track of the changes, a revision number is assigned to the original design and to each subsequent iteration. The original release might be called 1.0 and the next release might be numbered 1.1 or 2.1, to designate, for instance, different types of engineering mask changes (e.g., metal-only or front-end-of-the-line device changes.) For tracking purposes and to facilitate automatic testing and debugging of the various versions that may be in production, a version number is coded into the chip's logic. This version number is typically encoded within fixed-value latches that are set to the appropriate logic one or zero values, representing the chip's version number. This is done by tying the latch's inputs to GND or VDD as required, typically using first-level (M1) metal or very-low metal that is locally made available to the circuit. The values of these latches are externally readable by test equipment via software, and hence the version number of the chip can be easily determined.

     Because the values of the latches are typically defined by M1 metal, any change or correction to the chip that could otherwise be implemented with metal levels above M1 must also include M1, if only to update the value of the latches in order to change the revision number.

     The present invention allowed the chip revision level to be updated by making a metal-level change on any one and only one of the available metals, obviating the need to change M1 if a change in M1 is not required. Thus if a chip design change can be implemented using only level M5, for instance, the application of this invention removes the need to also change level M1.

     Since the invention allows easy changes in any layer of metal, the benefits of the invention and its attendant cost savings are considerable. For all engineering changes (ECs) that do not also require an M1 change, the cost of the M1 mask or reticle is saved. The savings amount to many thousands of dollars per reticle. The invention also removes the need to start wafers at M1 in order for the new revision number to be reflected on the chip. Thus wafers that are on hold at...