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CACHE CONTROL IN A NON-VOLATILE MEMORY DEVICE

IP.com Disclosure Number: IPCOM000147008D
Publication Date: 2007-Mar-04
Document File: 16 page(s) / 93K

Publishing Venue

The IP.com Prior Art Database

Abstract

A flash memory device includes a storage area having a main memory portion and a cache memory portion storing at least one bit per cell less than the main memory portion; and a controller that manages data transfer between the cache memory portion and the main memory portion according to at least one caching command received from a host. The management of data transfer, by the controller, includes transferring new data from the host to the cache memory portion, copying the data from the cache memory portion to the main memory portion and controlling (enabling/disabling) the scheduling of cache cleaning operations.

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CACHE CONTROL IN A NON-VOLATILE MEMORY DEVICE

FIELD OF THE INVENTION

    The present invention relates generally to the field of non-volatile memory devices. More particularly, the present invention relates to controlling operation of a cache memory implemented in a non-volatile memory device.

BACKGROUND OF THE INVENTION

    In the present invention the terms "memory" and "storage" are used interchangeably and have the same meaning. Consequently compound phrases containing those two terms (like "memory device" and "storage device", or "memory system" and "storage system") also have the same meaning.

    In the present invention the terms "controlling mechanism" and "controller" are used interchangeably and have the same meaning.

    A flash memory system implemented as a Multi-Level Cell (MLC) flash memory is provided for storing more than one bit of data on each memory cell. The writing of data into an MLC flash memory is typically slower than the writing of data into a Single- Level Cell (SLC) flash memory that stores only one bit of data per cell. Therefore, a storage system based on an MLC flash memory might not be capable of recording a stream of incoming data transmitted to it at a higher writing rate.

    Typically in cases where data is produced at a rate too high to be directly stored, a cache memory mechanism is provided and designed to operate fast enough to handle the incoming data stream. The cache memory utilizing a second (and faster) memory is implemented between the input data source and the main (and slower) memory of the flash memory device. The input data stream is first written into the faster cache memory, and at a later stage is copied from this faster cache memory into the main memory. As the copying operation between the cache memory and the main memory is typically performed in the background, this operation does not have to meet the strict performance conditions imposed by the input data stream rate, and therefore the lower write performance of the main memory is no longer an obstacle.

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    However, the implementation of a second memory for caching has its drawbacks. Such implementation requires additional components for the cache memory and its control, whereby complicating the design and management of the memory system.

    The prior art include US Patent No. 5,930,167 to Lee et al., which discloses a memory method and system for caching write operations in a flash memory storage system while achieving the benefits of caching in MLC flash memories but with less of the disadvantages. The MLC flash memory media of the Lee patent is configured to operate as its own cache memory. This is possible since memory cells that store multiple bits can be further implemented to operate similar to SLC memory cells and store only a single bit each, which is an easier task from a technological p...