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IP.com Disclosure Number: IPCOM000147009D
Publication Date: 2007-Mar-04

Publishing Venue

The IP.com Prior Art Database


To read one or more flash memory cells, the threshold voltage of each cell is compared to at least one integral reference voltage and to at least one fractional reference voltage. Based on the comparisons, a respective estimated probability measure of each bit of an original bit pattern of each cell is calculated. This provides a plurality of estimated probability measures. Based at least in part on at least two of the estimated probability measures, respective original bit patterns of the cells are estimated. Preferably, the estimated probability measures are initial probability measures that are transformed to final probability measures under the constraint that the bit pattern(s) (collectively) is/are a member of a candidate set, e.g. a set of codewords.

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    The present invention relates to storage of data in nonvolatile memories such as flash memories and, more particularly, to a method of reading data stored in a flash memory by reading both hard bits and soft bits and then jointly decoding all the read bits.

    Originally, flash memories stored only one bit per cell. Flash memories that store two bits per cell now are available commercially, and flash memories that store more than two bits per cell are being developed. Flash memories that store one bit per cell are called "Single Level Cell" (SLC) memories. Flash memories that store more than one bit per cell are called "Multi Level Cell" (MLC) memories.

    Figure 1 illustrates how a bit pattern of three bits is stored in a MLC memory that is capable of storing three bits per cell.

    A flash memory cell is a transistor with two gates: a conventional control gate and a floating gate. Data are written to the cell by injecting electrons into the floating gate. These injected electrons oppose the "reference" voltage that is applied to the control gate, and the cell does not conduct unless the reference voltage is sufficiently high to overcome the charge on the floating gate. The lowest reference voltage that is sufficiently high to overcome the charge on a flash memory cell's floating gate is called the cell's "threshold voltage" herein.

    The threshold voltage of a flash memory cell is in a range, called the "voltage window", from a minimum value Vmin to a maximum value Vmax. For historical reasons, writing data to a flash cell is called "programming" the flash cell. This is done by applying voltage pulses to the cell, to inject electrons from the cell's silicon

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substrate through the cell's oxide layer into the cell's floating gate, until the threshold voltage of the cell is higher than a "verify" voltage level associated with representation of the desired bit pattern. (The verify voltage level is called a "verify" voltage level because programming the cell includes verifying that the cell's threshold voltage exceeds this level.) In a three-bit-per-cell memory, the voltage window is divided into eight voltage bands: from Vmin to V1, from V1 to V2, from V2 to V3, from V3 to V4, from V4 to V5, from V5 to V6, from V6 to V7 and from V7 to Vmax. A threshold voltage within one of the voltage bands represents a bit pattern as shown in Figure 1: a threshold voltage between Vmin and V1 represents the bit pattern "111", a threshold voltage between V1 and V2 represents the bit pattern "110", etc. In general, the voltage window of a m-bit-per-cell memory is divided into 2m voltage bands.

    To read a flash cell, the threshold voltage of the flash cell is compared to the reference voltages that define the voltage bands. (These...