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An Efficient and Exhaustive Flow to Account for On-Chip-Variation in Static Timing Analysis

IP.com Disclosure Number: IPCOM000147424D
Publication Date: 2007-Mar-14
Document File: 4 page(s) / 141K

Publishing Venue

The IP.com Prior Art Database

Abstract

As technology shrinks, sensitivity due to PVT (process, voltage, temperature), On-Chip Variation (OCV) is increasing. It is becoming increasingly important to incorporate the impact of OCV in Static Timing Analysis (STA). The common approach of applying a figure of 10-20% globally to account for OCV is highly pessimistic. At the same time, Location Aware OCV requires an excessively long run-time.

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An Efficient and Exhaustive Flow to Account for On-Chip-Variation in Static Timing Analysis

Abstract

As technology shrinks, sensitivity due to PVT (process, voltage, temperature), On-Chip Variation (OCV) is increasing. It is becoming increasingly important to incorporate the impact of OCV in Static Timing Analysis (STA).  The common approach of applying a figure of 10-20% globally to account for OCV is highly pessimistic.  At the same time, Location Aware OCV requires an excessively long run-time.

This paper presents a cogent flow to account for On-Chip Variation in STA that overcomes the drawbacks of existing flows.

Body

Conventional Flow/Practice

Why OCV?

In conventional corner-based STA,

    a) Timing is checked at two or more extreme PVTs.

    b) Timing characteristic of two instances of any standard cell is considered to be same at a specific PVT.

The assumption is true if intra-die variation doesn't exist. But, as we move towards sub-micron technologies, variation is becoming significant, which makes the timing analysis done on the chip inaccurate and results in unexpected setup/hold violations in silicon.  The process variation in gate delay can be observed in the graph shown in FIG. 1.


                 Figure 1: Gaussian distributions for a manufacturing process for a single worst case chip

POPULAR SOLUTIONS

Global Derate

To account for the variation in PVT, the common solution used by designers is global derate.  In this process a fixed derate factor (typically 10-20%) based on the worst possible timing variation is calculated and applied to the cells and nets.

Limitations of Global Derate Method

Applying a 10-20% global derating to the analysis is highly pessimistic.  It assumes same sensitivity to PVT variation for every cell instance and does not take into account the physical location of these cells on the die.  This leads to over designing in terms of area and power.

Location Aware On Chip Variation

The procedure to account for OCV as a function of distance (LOCV) follows.

 

  1. While analyzing paths, maximum distance between any pair of launch and capture path cells is calculated.
  2. Using the variation distribution curve and maximum distance, derate is calculated for all the cells in that...