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SUBMICRON SYSTEMS ARCHITECTURE Semiannual Technical Report

IP.com Disclosure Number: IPCOM000147866D
Original Publication Date: 1986-Mar-31
Included in the Prior Art Database: 2007-Mar-28
Document File: 66 page(s) / 4M

Publishing Venue

Software Patent Institute

Related People

Seitz, Charles L.: AUTHOR [+2]

Abstract

SUBMICRON SYSTEMS ARCHITECTURE Semiannual Technical Report Department of Computer Science California Institute of Technology 5220:TR:86

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SUBMICRON SYSTEMS ARCHITECTURE Semiannual Technical Report Department of Computer Science California Institute of Technology

5220:TR:86

March 1986

Reporting Period: 16 September 1985 to 15 March 1986

Principal Investigator: Charles L Seitz

Faculty Investigators: James T Kajiya

Alain J Martin

Robert J McEliece

Martin Rem

Charles L Seitz

Sponsored by the


Defense Advanced Research Projects Agency ARPA Order Number 3771

Monitored by the

   
Office of Naval Research
Contract Number N00014-79-0597

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SUBMICRON SYSTEMS ARCHITECTURE

Department of Computer Science

California Institute of Technology

1. Overview and Summary

1.1 Scope of this Report

  This document is a summary of the research activities and results for the six month period 16 September 1985 to 15 March 1986 under the Defense Advanced Research Project Agency (DARPA) Submicron Systems Architecture Project. Tech- nical reports covering parts of the project in detail are listed following these sum- maries, and can be ordered from the Caltech Computer Science Library.

1.2 Objectives

  The central theme of this research is the architecture and design of VLSI systems appropriate to a microcircuit technology scaled to submicron feature sizes, and includes related efforts in concurrent computation and VLSI design.

  Additional background information can be found in previous semiannual tech- nical reports [5052:TR:82], [5078:TR:83], [5103:TR:83], [5122:TR:84], [5160:TR:84], [5178:TR:85], [5202:TR:85].

1.3 Highlights

Some highlights of the previous 6 months are:

Working Mosaic A elements (2.2 and 4.1)!!!

Torus Routing Chips work on first silicon (4.2).

Mosaic C - an SCMOS Mosaic element - being designed (2.2.2 and 4.3).

Compilation method for designing self-timed circuits (4.5).

128-node Intel iPSC in routine operation and available for use via the ARPAnet
(2.1.3).

New results in parallel execution of logic programs (3.1).

A new flow framework for concurrent programming (3.3)

Event-driven simulations chew up endless cycles on the cosmic cubes (3.5).

A surprise about network topologies (3.6).

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2. Architectural Experiments

2.1 Cosmic Cube Project

W C Athas, Michael Lichter, Wen-King Su, Chuck Seitz

  The cosmic cubes are working reliably, and researchers are using them for a p plicat ion programming projects and for event-driven simulations of other message- passing architectures. Usage has been moderately heavy, and there have been very few problems reported.

2.1.1 Hardware Status

  The &cube interface was moved from sol.caltech. edu, our main SUN file- server, a SUN-21170, to ceres, a SUN-21120, in order to lighten the load on the already overloaded file server. The 3-cube interfac...