Browse Prior Art Database

SUBMICRON SYSTEMS ARCHITECTURE Semiannual Technical Report

IP.com Disclosure Number: IPCOM000147877D
Original Publication Date: 1988-Apr-07
Included in the Prior Art Database: 2007-Mar-28
Document File: 30 page(s) / 2M

Publishing Venue

Software Patent Institute

Related People

Seitz, Charles L.: AUTHOR [+2]

Abstract

Department of Computer Science

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 5% of the total text.

Page 1 of 30

SUBMICRON SYSTEMS ARCHITECTURE Semiannual Technical Report

Department of Computer Science
California Institute of Technology

Caltech-CS-TR-88-5

7 April 1988

Reporting Period: 1 November 1987 - 31 March 1988

Principal Investigator: Charles L. Seitz

Faculty Investigators: William C. Athas
K. Mani Chandy Alain J. Martin

Martin Rem

Charles L. Seitz

Sponsored by the!

Defense Advanced Research Projects Agency DARPA Order Number 6202

Monitored by the

    
Office of Naval Research
Contract Number N00014-87-K-0745

[This page contains 1 picture or other non-text object]

Page 2 of 30

[This page contains 1 picture or other non-text object]

Page 3 of 30

SUBMICRON SYSTEMS ARCHITECTURE

Department of Computer Science

California Institute of Technology

1. Overview and Summary

1.1 Scope of this Report

  This document is a summary of the research activities and results for the five- month period, 1 November 1987 to 31 March 1988, under the Defense Advanced Research Project Agency (DARPA) Submicron Systems Architecture Project. Previous semiannual technical reports and technical reports covering parts of the project in detail are listed following these summaries, and can be ordered from the Caltech Computer Science Library.

1.2 Objectives

  The central theme of this research is the architecture and design of VLSI systems appropriate to a microcircuit technology scaled to submicron feature sizes. Our work is focused on VLSI architecture experiments that involve the design, construct ion, programming, and use of experimental message-passing concurrent computers, and includes related efforts in conculrrent computation and VLSI design.

1.3 Highlights

Some highlights of the previous five months are:

The Ametek Series 2010, a second-generation medium-grain multicomputer developed as a joint project between our research project and Ametek Computer Research Division, was announced as a commercial product. A 16node engineering prototype has been demonstrated running numerous application programs. (See section 2.1 and the paper "The Architecture and Programming of the Ametek Series 2010 Multicomputern in the appendix.)

Enhancements to the Cantor programming system (section 3.1).

Reference definition of the functions of the Cosmic Environment and Reactive Kernel (sections 3.2 and 3.3).

High-quality self-timed VLSI designs are being produced by a compilation procedure that is now fully automatic (sections 4.1 and 4.2).

Fast "Mesh Routing Chips" (section 4.5).

[This page contains 1 picture or other non-text object]

Page 4 of 30

2. Architecture Experiments
2.1 Second-Generation Medium-Grain Multicomputers*
Chuck Seitz, Alain Martin, Bill Athas, Charles Flaig, Jakov Seizovic, Craig Steele, Wen-King Su

  On 19 January 1988, the Ametek Series 2010 multicomputer was announced at the 1988 Hypercube Conference in an invited talk by Chuck Seitz. This is the first m...