A COMPARISON OF TWO MICROPROGRAMMABLE PROCESSORS: PDP-11/40E AND MLP-900.
Original Publication Date: 1975-May-31
Included in the Prior Art Database: 2007-Mar-28
Software Patent Institute
Oakley, John D.: AUTHOR [+2]
A COMPARISON OF TWO MICROPROGRAMMABLE PROCESSORS: PDP-l.I/4OE AND MLP-900. John D. Oakley
A COMPARISON OF TWO MICROPROGRAMMABLE PROCESSORS: PDP-l.I/4OE AND MLP-900.
John D. Oakley
Department of Computer Science
Pittsburgh, Pa. 15213
A study was undertaken to evaluate the capabilities of two microprogrammable processors: the MLP-900, a vertically-encoded 36-bit machine at the Information Sciences .Institute and available over the ARPA Network; and the PDP-11/4OE, a horizontally-encoded 16-bit microprocessor at Carnegie-Mellon University. The paper presents a description of the two machines, and compares their performance an a number of 'benchmark programs (including an emulator for the NOVA computer), In addition, the machines are compared along dimensions of two-way conditional branch costs, basic architecture, and difficulty of programming. The POP-11/4OE performed between 102 and 25% faster on all the benchmarks except the multi-word integer multiply, where the MLP-900 was four times faster (because of its wider data path).
This ,work is supported by the Advanced Research Projects Agency (ARPA) of the Oepar t rnent of Defense, under contract F44620-73-C-0074, monitored by the Air Force Office of Scientific Research.
A Comparison of Two Microprogrammable Processors
The ongoing project at Carnegie-Mellon University investigating the symbolic manipulation of computer descriptions (SMCD) has the following primary goals: to design a language able to describe precisely an arbitrary target machine in a convenient fashion [I];
to create a compiler for this language which will transform a source machine description into a more usable representation; and to utilize .this compiled machine description in a range of applications, from computer-aided machine design to efficient compiler-compilers 12) A multi-level simulator for the target machine, capable of operating on the gate level, regiser-transfer level, or functional level, is also being designed, and will be important in many of the applications. This simulator will be implemented on a microprogrammable processor for efficiency reasons. Eventually, an optimizing micro-compiler will be developed whch will automat~ically produce an efficient simulator directly from a compiled target machine descviption.
Two possible machines for the simulator are currently being considered. The
first is the MLP-900, a vertically-encoded microprogrammable processor which exists at the Infarmation Sciences Institut'e at USC and is available over the ARPA Network. The second is a PDP-11/40, a horizontally-encoded microprogrammable processor, which has been modified at CMU to include a read/write control memory and other hardware extensions to make it a general purpose micropro...