Browse Prior Art Database

RAPIDbus Architecture and Realization

IP.com Disclosure Number: IPCOM000147974D
Original Publication Date: 1982-Nov-30
Included in the Prior Art Database: 2007-Mar-28
Document File: 90 page(s) / 6M

Publishing Venue

Software Patent Institute

Related People

Willis, John C.: AUTHOR [+3]

Abstract

Architecture and Realizatidn Abstract I RAPIDbus. Architecture and Reolwrion describes a synchronous multiprocessor dbigsigned LO s~pport sensory processing, image understanding, and control applications. Up to eight board levdl masters interact with up to eight slaves along a time-multiplexed implementation of a crossbar switch. two implementations are considered, one based on an Advanced Shottky logic with a bus bandwidth of-16 r[hz and a Versabus host interface. The second implementation, based on an ECL/TXZ gate array, permits estimated 64 hIIu of bus bandwidth and a Versabus/Multibus host interface. Segmented memory managemienti a multicast capability between one master and multiple destinations, and a standardized host interface ai4 in making RAPIDbus an appropriate architecture for robotic applications. I I I This research was support by the National Science Foundation under grant number $CS-7923893. I "P John C. Willis Dr. Arthur C. Sanderson The Robotics InstituteCarnegie-Mellon UniversityPittsburgh, Pennsylvania 15213

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Architecture and Realizatidn

Abstract ! I

RAPIDbus. Architecture and Reolwrion describes a synchronous multiprocessor dbigsigned LO s~pport sensory

processing, image understanding, and control applications. Up to eight board levdl masters interact with up to eight slaves along a time-multiplexed implementation of a crossbar switch. two implementations are
considered, one based on an Advanced Shottky logic with a bus bandwidth of-16 r[hz and a Versabus host interface. The second implementation, based on an ECL/TXZ gate array, permits estimated 64 hIIu of bus

"P

bandwidth and a Versabus/Multibus host interface. Segmented memory managemienti a multicast capability between one master and multiple destinations, and a standardized host interface ai4 in making RAPIDbus an appropriate architecture for robotic applications.

I

I

I

This research was support by the National Science Foundation under grant number $CS-7923893.

I

John C. Willis

  
Dr. Arthur C. Sanderson
The Robotics Institute
Carnegie-Mellon University
Pittsburgh, Pennsylvania 15213

November 1982

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RAPIDbus: Architecture and Realization

7.1 System Timing
7.1.1 The Master
Clock
7.1.2 The Window Address System
7.1.3
The Host Clocks
7.2 Control Lines
7.2.1 ACCLK
7.2.2 Reset
7.2.3 Test
Configuration Lines
7.2.4 ACFAIL
7.3
I/O Interface
7.3.1
I/O Bus
7.3.2 Serial Access

8. Where Next?
I. Connector CP1 Signals
11. Connector CP2 Signals

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RAPIDbus: Architecture and Realization

List of Figu res

Figure 1-1: The interconnection scheme for a multiprocessor system can havb a heavy effect on system efficiency.

Figure 1-2: Common bus architectures trade off simple hardware for increasedlbus contention in a multiprocessor system. I

Figure 1-3: Multipart Memory reqJires a unique link between each processOK and one or more system memory arrays. 1

Figure 1-4: Crossbar switching permits multiple connections between process04 and memory to be made randomly and simultaneously, but requires complex hardware!

Figure 1-5: A time multiplexed common bus structure allows multiple simulta&ous random paths with a switching circuit that grows in switch bandwidth and not Nŝbitch complexity as does a crossbar switch. ,

Figure 1-6: A Rapidbus system is composed of many independent elements.

Figure 3-1: The virtual bus system is implemented using bus windows to link Fveral masters and several slaves simultaneously
Figure 3-2: Each RAPIDbus interface card is composed of multiple modules, cdntered arounithe

Ibus.

Figure 3-3: Several multicast address generators are needed to create the hll address range required for a memory access....