Browse Prior Art Database

A High Speed Processor for Binary Images

IP.com Disclosure Number: IPCOM000148159D
Original Publication Date: 1984-Feb-29
Included in the Prior Art Database: 2007-Mar-29

Publishing Venue

Software Patent Institute

Related People

Berger, Robert W.: AUTHOR [+2]

Abstract

A High Speed Processor for Binary lmagesl CM U-K

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 26% of the total text.

Page 1 of 18

A High Speed Processor for Binary lmagesl

1-'l'R-84s.2

Inspcction Laboratory

  The Robotics Institute Carnegic-Mellon University
Pittsburgh,
Pennsylvania 15213

February 1984

Copyright @ 1984 Carnegie-Mcllon University

This research was supported by thc Robotics Institutc, Carncgic-Mellon University.

This paper appcarcd in Proceedings of he IEEE Cornpurer Society Conference on mputer Vision and Pattern Recognilion 83. Washington, D. C., June 1983.

4

CM U-K

[This page contains 1 picture or other non-text object]

Page 2 of 18

[This page contains 1 picture or other non-text object]

Page 3 of 18

[This page contains 1 picture or other non-text object]

Page 4 of 18

[This page contains 1 picture or other non-text object]

Page 5 of 18

List of Figu res

Figure 3-1: Data Path for One Row of the Operator Kern1 .

. Figure 3-2: Data path for thc Convolution Processor
Figure 3-3: Architecture of the Real-'Time Vision System
Figure 5-13: Charactcr ltccognition Example - Input
Figure 5.1 b: Character Rccognition Example - Mask
Figure 5-lc: Character Recognition Example - Correlation Figure 5-1 d: Character liccognition Example - 'il.lrcsholdcd Figure 5-2a: Printed Wiring Example - Input
Figurc i2b: Printed Wiring Example - Mask
Figure 5-2c: I'rintcd Wiring Examplc - Convolution
Figurc 5-2d: Printed Wiring Example - 'i'hrcslioldcd Convolution

[This page contains 1 picture or other non-text object]

Page 6 of 18

[This page contains 1 picture or other non-text object]

Page 7 of 18

Abstract


A video rate processor for binary images is described in this paper. The

a 3 level 64 by 64 mask. Images are processed at a rate of 10 million processing of images obtained from a CCD camera.

with time

[This page contains 1 picture or other non-text object]

Page 8 of 18

[This page contains 1 picture or other non-text object]

Page 9 of 18

1. Introduction

In this document we describe the design of an image proccssor for binary images.

processed at vidco rates. ?'he proccssing consists of convolving thc input irnagc with operator kcrncl.

 ?'he convolution of a discrete two-dimensional imagc array I(x,y) with a 2 N f 1 Kfi, j) yielding an output irnagc O(x,y) is given by

N N

The dcvice is used as a

preprocessor in a computcr vision system. Toc input image is obtained directly from solid statc camera and

in the systcm dcscribed, thc input image l(x,y) is a binary imagc consisting of twc IcvcIs, 1 and -1. 'The opcrator kcrncl K(i,j) is a M by 64 arrayx whosc clcmcnts are rcstrictcd to bc O's, 1

1

                                             s, and -1's. 'Ihc input image is 2048 pixcls widc and arbitrarily long. 'l'he irnagc is obtaitlcd by a linear CCD a ray solid statc camcra. The device can process 10 million pixcls pcr sccond.

i

2. Background

'I'hc convolution opcration dcscribcd by equation 1 can bc exyrcssed as a corrclation ith a mask Kf(i,j)

wherc thc orrclation mask K'(ij) is the convolution mask of...