Method for partitioning the difference between hardware and specification electrical parameters into geometric and electrical components.
Original Publication Date: 2007-Mar-29
Included in the Prior Art Database: 2007-Mar-29
A method to determine the electrical characteristics of semiconductor devices at specified geometries by interpolation of measurements at other geometries.
Method for partitioning the difference between hardware and specification electrical parameters into geometric and electrical components .
The procedure assumes that the actual dimension of the measured devices are known using one the many published methods of determine FET length and width. The interpolation is done logarithmically on the electrical parameter so that parameters such as off-current, which can vary by more than an order of magnitude, scale reasonably. Other parameters which vary in a much tighter range give similar results for either linear or logarithmic scaling. The geometrical scaling is done in reciprocal dimensions reflecting the general accelerating trend at short dimensions.
To do the interpolation 3 measured devices are used which satisfy the following relationships:
L1 = L2
L2 not equal L3
W1 not equal W2
W2 = W3.
The three devices are choosen from the available devices so that L2 and W2 are as close as possible the specified L and W.
A correction to the measurement on device W2/L2 is calculated based on interpolation in length between L2 and L3 to the specified L. A separate correction is calculated based on interpolation in width between W2 and W1 to the specified W. The two correction are applied to the measured electrical characteristic of device with dimensions W2/L2. The corrected electrical measurement can be compared to the specified value W/L and will contain only minimal residual error due to...