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Wafer-Scale Integration of Systolic Arrays Disclosure Number: IPCOM000149099D
Original Publication Date: 1899-Dec-30
Included in the Prior Art Database: 2007-Apr-12
Document File: 64 page(s) / 4M

Publishing Venue

Software Patent Institute

Related People

Leighton, Frank Thomson: AUTHOR [+3]


Welder-Scale Integration of Slystolis: Arrays h%bematicns Department and Laborabv for Cornpub !Science MassachursettÎnstitute of Teehnolom

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Welder-Scale Integration of Slystolis: Arrays

    h%bematicns Department
Laborabv for Cornpub !Science MassachursettÎnstitute of Teehnolom

Cambridge, Massaehu~ettns 02139

Charles E, Leiwr~an

Laboratory for Compubr !Sciace

Masexhusette Hnxtituk of Technoloa
mesacbchuseBs 01138

  Abstract: VLSB klnnolo@sts are fast de'vdoping wfer-scale hiegation. Rsatliser tbzm par- titioning a dieon -#afer into chipga mi isa nsudly do~se, %be idea behind wder-~de inbgra~oail L

to as~mble entire s:rskmrs (or nehork of chips) on a 4~;gBe

                                      wafer, thus avoi&ng the m&e md performanee Ioens msocia~ted with indiv;ldud p a c h a g of chips. A =jar probllem with wwmbEng
as large ~yskw
of ~eroproceewar~
an a iagle wafer, bowever, is that wme d the proeesmr8, or cells, on &he wafer are likely to be defwltive. h the paper, we desc~be
pracGaB proedmw for integrating wder-wde qsbw5 usround" such hulks. That predures me dedgnd ta d d ~ s e the length of the longed wire in the q;qresbm, thus ~nidlsing
the mmmu~ation
time be

cells. Nthsugla the underlying network problem^ me Weompleh, we prove that %be p r o d w a are reliable by assuminng a probabilistic model of cell faiilwe. We dso discuss spp&a~one sf

%his work ta prob%ems in PLSB layout theo~)~,
graph awby9 fauP$-bIeran q~hrns
ad plmaa


Key Worels: chmg~al vsridth, faul$bleranat qslems, probabilidic mdy&~,

ke, ryc

problem, tree of naesher;, VLSI, wder-de bkgpa~on,

W e


Charles Leisernon ia a pnrdrtirne eon~~ulhnt
for Lincoln BLabQrub~y. A preliminary version of Mr piper

appeared in the 8982 EEE Foundlsrtions d CQmpukr $cience anfe~mm.


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1. Introduction

  VLSH techleologists are fast devdoping wafer-sesle integration [30]. Rather %ban partitioning s silicon wafer into chips as is usually done, the idea behind wafer-scale integration is ta assemble an eatire sy5tern (or nett4r~bl.k of chips) on a 8ing'Be wafer, thus avoiding the costs and performance loss associated ~ t h
individual packaging of chip. A major problem with assembling a large system of microprocessore on a ingle wafer, however, is that mme 0% the gracesmrs, or: eelis,

OHI the wafer are 3ikdy $o be defective. Thus a practical prolcedure for inkgrating wder-~de qstems must have the abi:,ity to conIigure networlts '6aarournd" such faults.

  This gaper considers ea, variety of problems involving &be construction of astonic arrays 8154. Systolic arrays are a desira1ca8e architeetanre for W,SI because all communication is betweĉnteeaaeet neighbors. In a wafer-~de
rsystem, however, all the nearest nejgbbors of a proceemr may be BeapB,

and thus the prime advantage OF adopting a $y~%oBic
array arcBitecture may be lo& if a Bong wire

connects adjacent processcbre. jfrn gener...