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INTRODUCTION TO THE THEORY OF SPEED INDEPENDENT ASYNCHRONOUS SWITCHING CIRCUITS

IP.com Disclosure Number: IPCOM000149506D
Original Publication Date: 1966-Jul-31
Included in the Prior Art Database: 2007-Apr-01
Document File: 31 page(s) / 1M

Publishing Venue

Software Patent Institute

Related People

Hall Jr,A.D.: AUTHOR [+2]

Abstract

A. D. Hall, Jr. This work was done while the author was a National Science Foundation Fellow. X1 zl Z lb 2 Out puts Z P Inputs X2 B X 3 m Combinational Network Y Y l .& Y 2 t '2 I d Yn ;) Delay . 6 I Delay Figure 1. Model for fundamental mode sequential circuits. change also. This process continues until the circuit becomes stable, at which time another change i n the inputs can take place. The output is determined from the values of the inputs and the values of the feedback loops. Synthesis procedures which are based on certain idealizing assumptions about the operation of the logic gates have been developedfor this type of circuit. The most common assumption, is that the delays associated with the logic gates and delays due t o wiring are small compared t o the delays in the feedback paths (shown by dotted lines in Fig. 1.) These feedback delays are under control of the circuit designer and canbe made large enough t o insure correct operation. Under this assumption the circuit can be designed as i f the gate and wiring delays are zero.

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Page 1 of 31

PRINCETON UNIVERSITY

Department of Electrical Engineering Digital Systems Laboratory Technical Report Number 5U

(July 1966)

INTRODUCTION TO THE THEORY OF SPEED INDEPENDENT ASYNCHRONOUS SWITCHING CIRCUITS

A. D. Hall, Jr.

This work was done while the author was a National Science Foundation Fellow.

[This page contains 1 picture or other non-text object]

Page 2 of 31

X1 *-

* zl

 Z
lb 2

Out puts

Z P

Inputs

X2 B

X 3 m

Combinational Network

Y

Y l .&

Y 2

t

'2

I

d

\

Yn ;)

---

-- -

Delay

.

6

I

Delay

Figure 1. Model for fundamental mode sequential circuits.

[This page contains 1 picture or other non-text object]

Page 3 of 31

change also. This process continues until the circuit becomes stable, at which time another change i n the inputs can take place. The output is determined from the values of the inputs and the values of the feedback loops.

      Synthesis procedures which are based on certain idealizing assumptions about the operation of the logic gates have been developed
for this type of circuit. The most common assumption, is that the delays associated with the logic gates and delays due t o wiring are small compared t o the delays in the feedback paths (shown by dotted lines in Fig. 1.) These feedback delays are under control of the circuit designer and can
be made large enough t o insure correct operation. Under this assumption the circuit can be designed as i f the gate and wiring delays are zero.

      Some of the problems which must be considered in the synthesis of this type of circuit are outlined below.

Races

      In the circuit of Fig. 1, a change of a single input, say x, may
cause two or more of the feedback paths to change value simultaneously.

This condition is called a race, and if correct circuit operation depends
on the order in which these changes reach the combinational network, then
the race is called critical. Huffman [33 has shown that races can be eliminated if a sufficient number of feedback paths are used in the realization.

Hazards

      Another difficulty which can cause incorrect circuit operation is the presence of static hazards [ s ] in the combinational circuitry. A com- binational network is said to contain a static hazard i f and only if there

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Page 4 of 31

exists a single input variable change for which the output before the change is equal to the output after th.e change, and during the change a momentary output pulse may occur.

      In the sequential circuit of Fig. 1, a change i n an input x, may cause a feedback path t o change value because a static hazard is present
in the combinational circuitry. Methods for eliminating such hazards have been developed by Caldwell 611, Muffman 151 and McCluskey [ 6 , 7 ] . It should be noted that static hazards do not exist i n the combinational network under the assumption that gate delays and wiring delays are zero. The...