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Discharge Control for Mixed Mode Multiplexer System

IP.com Disclosure Number: IPCOM000149782D
Publication Date: 2007-Apr-05
Document File: 3 page(s) / 56K

Publishing Venue

The IP.com Prior Art Database

Abstract

A mixed mode multiplexer system consists of an analog mode switch powered by 2.5v VCCA and a digital mode switch powered by 0.9v VCCD. The analog mode switch is a low dropout voltage regulator; the digital mode switch is a stack of two PMOS in series. Different output voltage levels are generated depending on chip operation sequences. Discharge sequence control for the mixed mode multiplexer is invented to avoid drain-bulk junction forward biasing on the digital PMOS switch during transition from analog mode to digital mode.

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Discharge Control for Mixed Mode Multiplexer System

 

Invention

A mixed mode multiplexer system consists of an analog mode switch powered by 2.5v VCCA and a digital mode switch powered by 0.9v VCCD. The analog mode switch is a low dropout voltage regulator; the digital mode switch is a stack of two PMOS in series. Different output voltage levels are generated depending on chip operation sequences. Discharge sequence control for the mixed mode multiplexer is invented to avoid drain-bulk junction forward biasing on the digital PMOS switch during transition from analog mode to digital mode.

When the multiplexer output voltage switches from 1.6v through the analog mode switch to 0.9v through the digital mode switch, there is drain-bulk junction forward biasing stress on the digital PMOS switch.  The advantage of this technique is that it prevents latch-up risk during transition from analog mode to digital mode.   

 

Implementation:

Figure 1 shows a mixed mode multiplexer system consisting of an analog switch and a digital switch. The purpose of this system is to produce a VCCVR output at 1.6v or 0.9v from 2.5v VCCA or 0.9v VCCD. The multiplexer power system can not be a pure analog system because there is a requirement that VCCVR must track closely with VCCD in some modes. Using an analog system to produce the VCCD voltage level is not a good solution due to a slow response of the negative feedback system compared to a fully pulled-up PMOS pass transistor. 

The analog switch is a low dropout voltage regulator powered by 2.5v VCCA. The voltage regulator is a negative feedback system comprised of an error opamp driven PMOS pass transistor. The output VCCVR is divided by half through a resistor divider and feedback node, VCCFB, to the positive terminal of the error opamp. The negative terminal of the error opamp is selected by SEL_MODE which selects between digital mode and analog mode. When SEL_MODE equals “1”, VREFIN will be connected to half of VCCD through a resistor divider. When SEL_MODE equals “0”, VREFIN will be connected to VREF which is generated from a reference voltage source such as a Bandgap or Multiplier. Reference input voltage VREF is 0.8v in order to generate VCCVR = 1.6v during analog mode operation. Error opamp is “on” or “off” based on enable signal EN. It will be on when EN = “1” and off when EN = “0”.

The digital switch is a stack of two PMOS in series. This scheme is designed to prevent source-bulk or drain-bulk junction’s forward biasing. If only MP2 is used, VCCVR = 1.6v and VCCD = 0.9v will cause drain-bulk junction to forward bias. If only MP3 is used, V...