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Optimization of EOR depths for DSB technology

IP.com Disclosure Number: IPCOM000165744D
Original Publication Date: 2008-Jan-03
Included in the Prior Art Database: 2008-Jan-03
Document File: 1 page(s) / 55K

Publishing Venue

IBM

Abstract

Disclosed is the optimal location for the end-of-range defects resulting from the fabrication of hybrid orientation Si wafers by direct-silicon-bonded (DSB) amorphization/templated recrystallization (ATR) methods.

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Optimization of EOR depths for DSB technology

    Hybrid orientation technology is desirable for its advantage of employing optimal crystalline surfaces for NFETs and PFETs, i.e., NFETs on Si (100) and PFETs on Si (110). Hybrid orientation substrates may be fabricated from direct-silicon-bonded (DSB) wafers using amorphization/templated recrystallization (ATR) techniques in which selected regions of the (110) DSB layer are changed from their original orientation to the (100) orientation of the base substrate. The resulting changed-orientation regions typically include a band of end-of-range (EOR) defects just below the amorphous/crystalline boundary created by the ion-implant-induced amorphization. These potentially problematical defects are shown to have a negligible effect when their location is properly optimized.

    In general, there are two types of defects of leakage concern in DSB technology: the defects at the (110)/(100) bonding interface in PFET regions and the end-of-range (EOR) defects at the bottom interface of the converted (100) NFET regions. The position of these defects in NFET regions may be optimized to minimize leakage current.

    The position of EOR defects with respect to the device region is depicted in the figure. There are four leakage components which may be affected by EOR defects: (1) STI peripheral junction leakage, (2) area...