Browse Prior Art Database

Method to detect erroneous Front Side Bus errors due to an asynchronous reset in a server system

IP.com Disclosure Number: IPCOM000166946D
Original Publication Date: 2008-Jan-29
Included in the Prior Art Database: 2008-Jan-29
Document File: 2 page(s) / 24K

Publishing Venue

IBM

Abstract

CPU monitor errors on Front Side Bus but there have been cases of false error reporting at reset because of the time it takes for all functional units like northbridge to propagate the reset request up to the CPU before the CPU stops looking for errors. Disclosed is a unique solution to the problem by filtering such errors signals in Baseboard Management Controller (BMC) with regard to reset signal and letting BIOS know when to ignore them as false errors.

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Method to detect erroneous Front Side Bus errors due to an asynchronous reset in a server system

When the System Management Interrupt (SMI) handler executes in BIOS and finds that the processor Machine Status Registers have recorded a machine check error, a message will be sent to the system management unit such as the Baseboard Management Controller (BMC) to verify if it has recognized an error and whether the platform reset was high or low at the time of recording the error. If the platform reset signal to the BMC was low at the time the Error signal from the NorthBridge is low then the BMC does not recognize that as a valid error and will return a non-error message. On the other hand if the platform reset was high and the Error from the North Bridge is low then it is a genuine system error and the BMC would inform the BIOS that the error is valid.

     The description of how the idea works is shown in the figure. The timing window where the error can occur is chipset and processor technology dependent.

RESET AT NORTH BRIDGE

TIMING WINDOW OF FALSE ERROR GENERATION

CPU DETECTING INVALID FSB AND

DRIVING MCERR

Clock

FSB Transaction FSB DRIVEN INVALID BY NORTH
BRIDGE

VALID FSB SIGNALS

CPU STILL ACTIVELY MONITORING FSB WHILE RESET IS STILL

PROPAGATED

RESET AT CPU

MCERR BY CPU

ERROR SIGNAL FROM NORTH BRIDGE

NORTH BRIDGE DRIVES ERROR SIGNALS

BMC MONITORS THE ERROR SIGNALS AND RESET SIGNAL.

ERROR VALID OR NOT MESSAGE SENT TO BIOS REQ...