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Novel Noise Cancellation Circuit for PLL Voltage Regulator

IP.com Disclosure Number: IPCOM000166949D
Publication Date: 2008-Jan-29
Document File: 9 page(s) / 385K

Publishing Venue

The IP.com Prior Art Database

Abstract

In prior-art PLL, voltage regulator is used to power sensitive analog core. The voltage regulator produces 1.65V on-chip which is PVT independent. Since the regulated voltage is used to power sensitive analog circuits, it need to have very low noise. This invention basically uses circuit technique to cancel out the regulated voltage noise, thus lower PLL jitter. Note that this invention is not limited to PLL voltage regulator; it can be used in any analog circuits that required low noises.

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Title of Invention:

Novel Noise Cancellation Circuit for PLL Voltage Regulator

Introduction:

            In prior-art PLL, voltage regulator is used to power sensitive analog core. The voltage regulator produces 1.65V on-chip which is PVT independent. Since the regulated voltage is used to power sensitive analog circuits, it need to have very low noise. This invention basically uses circuit technique to cancel out the regulated voltage noise, thus lower PLL jitter. Note that this invention is not limited to PLL voltage regulator; it can be used in any analog circuits that required low noises.

PLL Regulator Architecture:

      PLL regulator regulates 2.5V Vcca to two regulated output of the same voltage. The regulated 1.65V is used to power PFD level shifter, charge pump, and VCO.

     

Fig. 1 Voltage Regulator Architecture

            Fig. 1 shows the voltage regulator architecture. The bandgap generator produces 1.2V reference voltage (PVT independent) to Vreg0. The op-amp with negative feedback basically acts as a voltage amplifier to generate 1.65V.

Vreg0 ≈ (1+R2/R1)*1.2V=1.65V

Vreg0 is used to power charge pump and VCO. It also used as reference to generate second regulated supply which powers PFD’s level shifter. This is for noise isolation which prevents PFD noise from coupled into charge pump and VCO.

Prior Art Voltage Regulator:

Fig. 2 Prior-art Voltage Regulator

Fig. 2 shows a prior-art voltage regulator. Native nmos acts like a source follower to provide low output impedance and good power noise immunity. Rmin is used as minimum current path for stability and Mmin is used to cut off the current path in power-down state. We can see that Vcca noise coupled into Vreg0 through native nmos parasitic Cgd.

It is interesting to note that Rmin and Mmin path has mild noise cancellation effect since nPD is powered by Vcca (PD=’1’ in power-down state). Anyway, the circuit topology is not effective at killing off high frequency noises due to following reasons:

Ø      Limited bandwidth of nPD caused by the inverter RC product, thus not effective at killing off high frequency noises.

Ø      Series Rmin dominate the resistance, thus suppress Mmin resistance modulation caused by nPD.

The second interesting observation is that Vreg0 PSRR is degraded with increased VCO loading. Increased VCO loading increases ID_native_nmos, thus increase its gm. Since gm = id/vgs, this implies equal Vgs noise will causes higher noise at Vreg0.

Note this simplified diagram doesn’t show all of the power-down circuits.

Prior Art Bandgap:

Fig. 3 Prior-art Bandgap

Fig. 3 shows prior-art bandgap circuitry. It is used to provide 1.2V reference voltage on-chip which is PVT independent. Again, Vcca noises can couple into Vbg. Since Vbg is used as Vreg0 reference, its noises will propagate to Vreg0.

Invention:...