Browse Prior Art Database

Flip Chip Die Structure Can Provide Higher Bump Reliability

IP.com Disclosure Number: IPCOM000166950D
Publication Date: 2008-Jan-29
Document File: 3 page(s) / 90K

Publishing Venue

The IP.com Prior Art Database

Abstract

This invention is to introduce flip chip die structure can achieve higher bump reliability. Main root cause of the bump crack in a flip chip package is due to induced stress from Coefficient of Thermal Expansion (CTE) mismatch between die (2.5 ppm) and substrate (~19 ppm). In order to improve bump reliability, CTE mismatch should be minimized.

This text was extracted from a Microsoft Word document.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 54% of the total text.

Flip Chip Die Structure Can Provide Higher Bump Reliability

This invention is to introduce flip chip die structure can achieve higher bump reliability.

Main root cause of the bump crack in a flip chip package is due to induced stress from Coefficient of Thermal Expansion (CTE) mismatch between die (2.5 ppm) and substrate (~19 ppm). In order to improve bump reliability, CTE mismatch should be minimized.

There are two ways to reduce CTE mismatch. Reducing CTE value of substrate and increasing CTE of silicon die. Many people have been trying to decrease CTE of substrate. However this effort is not successful. Because substrate is composite material made by copper, glass fibers and fillers and resins. All those materials have different CTE value. It is very hard to control overall effective CTE of the substrate.

For silicon die case, CTE can be controlled by plating or attaching metal. Depending on material properties (modulus & CTE) and thickness of metal, effective CTE of die can be decreased. It will reduce CTE mismatch and provide better bump reliability.

Summarize what has been done before in the following provided space:

To improve bump crack reliability, following are evaluated:

Different underfill material / TIM material  / Low CTE substrate / UBM & SMO size …

Describe the problem(s) you are trying to solve in the following provided s...