Method and Concept of Solving Differential Charge Build-up thru Decoupling Capacitor Power Rail Sharing
Original Publication Date: 2008-Feb-04
Included in the Prior Art Database: 2008-Feb-04
Decreased chip yield is due to transistor device damage when there is differential charge build-up between power grid islands during manufacturing. This is solved by
Method and Concept of Solving Differential Charge Build -up thru Decoupling Capacitor Power Rail Sharing
Decreased chip yield is due to transistor device damage and in particular, from damage of devices from differential charge build-up between power islands during manufacturing. This problem is called "Antenna Problems". The current solution is running checks that are developed to detect potential Antenna Violations prior to releasing a chip design to manufacturing. It is not uncommon for these Antenna Checks to report hundreds of thousands of violations. Some of the violations may take a significant amount of resource to fix.
During manufacturing, charge is built-up from charged ions on interconnected topologies. If a connection exists between electrically isolated power grids or islands on the gates of a device, the differential may result in a current flow that damages the gate resulting in a decrease in chip yield.
Antenna Problems occur during the wafer build process. As wafers are manufactured, each layer is built one at a time from the bottom-up, meaning from the lowest level of metal to the highest level of metal. The chip design typically includes a "Power Grid" i.e. a structured grid of widths and spacings on orthogonal layers of metal. The power grids are typically more fully connected on the top layers of metal and are more fragmented on the lower layers of metal. Isolated power grids are created during the creation of the lower metal layers. The metal layers are built using charged ions. Due to the topology of the isolated power grids, different charges can be built up. When the isolated power grids are connected through devices and wires, the differential current can damage the gate device as shown in Figure 1.
Figure 1: Antenna Problem
Power Grid island are seen as chip is built until higher metal layers are added.
Vdd Power Grid island A Contains Large amount of Charge
Vdd Power Grid island B contains Small amount of charge
Current from High to Low charge Current can go through devices and cause damage
This is just one example of many possible paths between the two grids that could cause damage to the chip
Damaged gates result in a loss of the chip decreasing chip yield and increasing cost per chip.
Checks are developed to detect potential Antenna Violations prior to releasing a chip design to manufacturing. It is not uncommon for these Antenna Checks to report hundreds of thousands of violations. Some of the violations may take...