Browse Prior Art Database

STI A method of avoiding livelock conditions within a processor core using programmable pattern­matching schemes

IP.com Disclosure Number: IPCOM000167260D
Original Publication Date: 2008-Feb-05
Included in the Prior Art Database: 2008-Feb-05
Document File: 2 page(s) / 43K

Publishing Venue

IBM

Abstract

This invention can be broken up into two parts: 1) how to detect a potential livelock, and 2) what to do when detection occurs. The advantage of this invention is that the livelock detection mechanism, and resultant algorithms to produce an action to avoid a deadlock, are all done internally to the processor, where the process is quicker and able to cover more scenarios.

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STI A method of avoiding livelock conditions within a processor core using programmable pattern-matching schemes

This invention can be broken up into two parts: 1) how to detect a potential livelock, and
2) what to do when detection occurs.

Detection mechanisms include pattern-matching algorithms to detect a problem sequence found in hardware. These algorithms can be programmable by a user, once a problem is detected, as an 'after-the-fact' mechanism to handle the livelock.

Potential actions to take to cure a livelock scenario within the processor are: go into a 'serialize' mode, completing only 1 instruction at a time, across 1 or multiple threads; stall for n (programmable) cycles at various points in the pipeline, such as a dispatch or issue point, for 1 or multiple threads; lower or raise a particular thread's priority; hold a particular instruction in an issue queue for n cycles before re-issuing; etc. Different actions may affect the performance of a processor in worse ways than others, so one could also employ multiple detection mechanisms, with increasingly worse performance along each step of detection, such as to minimize the performance penalty associated with the first level of detection which would likely occur more often.

The advantage of this invention is that the livelock detection mechanism, and resultant algorithms to produce an action to avoid a deadlock, are all done internally to the processor, where the process is quicker and able to cover more scenarios.

The idea is to provide hardware mechanisms to enable many different possible pattern-matching algorithms to detect a potential sequence that may cause a livelock. The more robust the hardware, the earlier the sequence may be detected, and the livelock may be stifled, resulting in better performance of handling potential livelock scenarios. As mentioned earlier, livelock problems in a processor core are usually foun...