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OCV DRIVEN PARTITIONING

IP.com Disclosure Number: IPCOM000167403D
Publication Date: 2008-Feb-12
Document File: 5 page(s) / 201K

Publishing Venue

The IP.com Prior Art Database

Abstract

Abstract: Most new products today are designed using Hierarchical Physical Design Methodology due to large gate counts, shorter turnaround times and last minute IP changes. Hierarchical design demands accurate timing and clock budgets for blocks (partitions) to ease quick convergence of the timing of design. On every integrated circuit today, all of the transistors, metal and vias are a little bit different from each other. Physical variation can be attributed to differences in areas such as lithography, etching, polishing, alignment, and gradients. In current budgeting methodology, variation is not considered or modeled by either EDA tools or designers. This leads to extra design effort, lower performance and penalty in the form of area and power (pessimistic budgeting). We present variation aware budgeting. This approach offers improved performance of the inter-partition paths, smaller area and power numbers.

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OCV DRIVEN PARTITIONING

Abstract: Most new products today are designed using Hierarchical Physical Design Methodology due to large gate counts, shorter turnaround times and last minute IP changes.  Hierarchical design demands accurate timing and clock budgets for blocks (partitions) to ease quick convergence of the timing of design.  On every integrated circuit today, all of the transistors, metal and vias are a little bit different from each other. Physical variation can be attributed to differences in areas such as lithography, etching, polishing, alignment, and gradients.  In current budgeting methodology, variation is not considered or modeled by either EDA tools or designers.  This leads to extra design effort, lower performance and penalty in the form of area and power (pessimistic budgeting).  We present variation aware budgeting.  This approach offers improved performance of the inter-partition paths, smaller area and power numbers.

Introduction:

The traditional flat submicron flow carries a higher risk of having to iterate all the way from the start of the behavioral specification of the design to correct timing or functional problems that appear after routing.  The flat submicron flow is also subject to memory limitations and long run times in multi-million-gate designs.  Establishing a hierarchical flow enables you to achieve timing closure of multi-million-gate designs efficiently and make incremental functional and timing fixes of individual blocks after timing closure.  Although the general idea of this Hierarchical approach is fairly simple, obtaining accurate and realistic budgets for timing and clock is really challenging and plays a key role in reducing iteration for timing closure when we assemble blocks together.

Variation is currently treated by Fabs, tools, and designers (in a very ad-hoc manner), by application of derates or margins on the full design.  This is done to overcome inability in the EDA world to model silicon variation accurately.  This is explained in the Fig 1.  By applying opposite deration on Capture and launch clock paths e.g. for Setup analysis we increase launch path delays and we decrease capture path delays.  In this way we add margin of X% non-common-clock-latency-capture-path plus Y% non-common-clock-latency-launch-path into each timing path.

                                                                         Fig. 1

            Margins eat up the performance of the system, increase area of the die, impacts the power (both dynamic and leakage) and most importantly can toss up the schedule (worst case delays delivery of product on right time).  Thus it becomes essential that we reduce impact of margin applied by keeping pre silicon data coorelated to post silicon dat...