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Automated Process and Method for Incorporating Netlist Changes into an Existing Design With Repeaters

IP.com Disclosure Number: IPCOM000168287D
Original Publication Date: 2008-Mar-05
Included in the Prior Art Database: 2008-Mar-05
Document File: 6 page(s) / 177K

Publishing Venue

IBM

Abstract

The MergeNetlist process provides a rapid solution for incorporating incremental, functional design changes in an already evolved physical design. It performs this operation by applying the new netlist to the current design and leaving as much of the evolved design as possible undisturbed. Previously, whenever design updates were introduced, the designer typically had to bring his logic changes through the entire physical design process. This caused a large amount of duplicate effort, was very time consuming, and prone to errors. Other alternatives include vendor tools such as Cadence's defEco process which will also apply new netlist changes to the latest design view. But this process does not address repeaters which are a key compenent in today's high speed vlsi designs. The option of stepping through the entire physical design process again is very time consuming and the Cadence process had very limited flexibility and still resulted in a substantial amount of lost workload. MergeNetlist adds flexibility by providing numerous benefits and features particularly in the area of repeaters and wires which I have not seen addressed by any other tool. The addition of repeaters to a design, for example, has become a key part of vlsi designs over recent years and it is crucial to iterate as less often as possible on such repeater solutions.

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Automated Process and Method for Incorporating Netlist Changes into an Existing Design With Repeaters

Main Idea

The MergeNetlist process provides a rapid solution for incorporating incremental, functional design changes in an already evolved physical design. It performs this operation by applying the new netlist to the current design and leaving as much of the evolved design as possible undisturbed. Previously, whenever design updates were introduced, the designer typically had to bring his logic changes through the entire physical design process. This caused a large amount of duplicate effort, was very time consuming, and prone to errors. Other alternatives include vendor tools such as Cadence's defEco process which will also apply new netlist changes to the latest design view. But this process does not address repeaters which are a key components in today's
high speed vlsi designs. The option of stepping through the entire physical design process again is very time consuming and the Cadence process had very limited flexibility and still resulted in a substantial amount of lost workload. MergeNetlist adds flexibility by providing numerous benefits and features particularly in the area of repeaters and wires which I have not seen addressed by any other tool. The addition of repeaters to a design, for example, has become a key part of vlsi designs over recent years and it is crucial to iterate as less often as possible on such repeater solutions.

     MergeNetlist works on two different design views - one being the new netlist (let's call it view1) and the other being the old view (view2). View1 is usually a bare-bones view of the logical netlist meaning that very little physical design work has been applied. Basically it's a logical netlist that has been imported to the physical design environment. View 2 can contain lots of physical design information behind it - block placement, the addition of repeaters (aka buffers), and routing information. The main objective of MergeNetlist is to apply the design changes in an incremental fashion to view2 while keeping intact as much of the placement, repeater, wiring, etc... information as possible.

     As mentioned above, the major advantage of MergeNetlist over other solutions is in the way it deals with repeaters. Repeaters are basically small circuits used to power up or redrive weak signals. They are used extensively in VLSI designs mainly because recent chip technologies cannot maintain wire performance as fast as they increase silicon performance. So designs get larger and more dense but wire performance gets only slightly better or remains the same, meaning that you need to power up signals more often. Repeater solutions in a design can become quite complex and require lots of optimization. In order to preserve as much as this information as possible, MergeNetlist allows yo...