Browse Prior Art Database

Methodology for Insitu Measurement and Evaluation of High-Density Electrical Connections

IP.com Disclosure Number: IPCOM000168300D
Original Publication Date: 2008-Mar-05
Included in the Prior Art Database: 2008-Mar-05
Document File: 4 page(s) / 174K

Publishing Venue

IBM

Abstract

Recent server hardware development has required the implementation of a new, high-speed, single-ended card-board interconnect system to satisfy high processor-memory-I/O bus signal rates. This lead to the need to evaluate and qualify this new technology in its application environment by exercising and acquiring electrical measurement data using specific product form factors that represent the application extremes (i.e., connector size, static & dynamic loading, plugging orientation, etc.) to ensure the interconnect?s performance satisfies the required long-term reliability requirements. Previously this testing was completed using uniquely developed test vehicles. These test vehicles were typically form-factor compatible card assemblies with custom internal wiring and added test connectors to monitor the mated connector interfaces. The employment of these test vehicles had a number of drawn backs, including; (1) cost to design the special cards, (2) cost to procure and assemble these cards and (3) inability to completely mimic the true assembly application, thereby leaving the effects of any design deltas (i.e., actual product vs. test vehicle) left to interpretation.

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Methodology for Insitu Measurement and Evaluation of High -Density Electrical Connections

Disclosed here is the development of a testing methodology that employs actual product to evaluate the reliability of high-speed interconnected interfaces. Specifically, the methodology provides (1) the utilization of as designed electrical interfaces (i.e., fabric buses, etc.) to monitor electronic assembly reliability, (2) the utilization of the higher-level assembly product hardware/environment as part of the same, (3) the application of measurement and shorting cards assembled to existing product interfaces to do same and (4) the ability to allow multiple assembly variables to be assessed and evaluated (e.g., but not limited to, raw card suppliers/fabrication lots, soldering assembly variations, connector rework process variations, connector mated interface design limits, inherent connector mechanical support features, etc.)

     Key advantages of this approach is the ability to eliminate complicated and unique test vehicle development and to most effectively depict the true application assembly conditions. In addition, by employing test cables to the aforementioned measurement cards, this methodology allows control of the connector durability cycles by allowing measurement read-outs to be made independently of test connector mating/plugging cycles. Once established, the overall assembly can be subjected to the defined series of reliability tests (e.g., Telcordia, Bell Core, etc.).

     The measurement methodology disclosed here utilizes product cards and the employment of relatively simple measurement and shorting cards, specifically designed to exploit the product's card-to-card interface buses. This is accomplished by interconnecting the module sites, card to card, via the card-board interconnect system
(i.e., card-to-card interface bus). As depicted below, these buses map from the modules sites to the card to board connector. To facilitate this, read-out and measurements cards (mounted to specific module sites) are deployed within the test Processor cage assembly. In doing so, the selection of specific module sites provides the ability to monitor significant number of the nets while effectively covering the majority of the length of the connector. For example, a high-end application has a total of eight interfaces that can be used to complete the overall path being monitored (see Fig 1).

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Fig 1

The monitored measurement loop is provided in Fig 2 (note, other renditions of said loop should...