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Asymmetrical Placement Concept of 4R.times.8 planar FBDIMMs

IP.com Disclosure Number: IPCOM000169376D
Original Publication Date: 2008-Apr-24
Included in the Prior Art Database: 2008-Apr-24
Document File: 3 page(s) / 142K

Publishing Venue

Siemens

Related People

Juergen Carstens: CONTACT

Abstract

FBDIMM (Fully-Buffered Dual In-line Memory Module) modules are high density memory modules that provide huge capacity and cost-efficiency. Basically, such memory modules comprise an AMB (Advanced Memory Buffer) chip that drives various memory chips (DRAMs - Dynamic Random Access Memories) on a circuit board. The AMB communicates with the memory chips using clock (CLK) signals, command address (CA) signals and chip select (CS) signals. For this purpose, the AMB chip drives two CLK buses on the left-hand side and two CLK buses on the right-hand side of the AMB chip, one CA bus on the left-hand side and to a second CA bus on the right-hand side of the AMB chip, and two CTRL buses on the left-hand side and two CTRL buses on the right-hand side of the AMB chip.

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Asymmetrical Placement Concept of 4R.times.8 planar FBDIMMs

Idea: Srdjan Djordjevic, DE-Muenchen

FBDIMM (Fully-Buffered Dual In-line Memory Module) modules are high density memory modules that provide huge capacity and cost-efficiency. Basically, such memory modules comprise an AMB (Advanced Memory Buffer) chip that drives various memory chips (DRAMs - Dynamic Random Access Memories) on a circuit board. The AMB communicates with the memory chips using clock (CLK) signals, command address (CA) signals and chip select (CS) signals. For this purpose, the AMB chip drives two CLK buses on the left-hand side and two CLK buses on the right-hand side of the AMB
chip, one CA bus on the left-hand side and to a second CA bus on the right-hand side of the AMB
chip, and two CTRL buses on the left-hand side and two CTRL buses on the right-hand side of the AMB chip.

The number of memory chips from which data (DQ) can simultaneously be read out in the event of a read access or the number of memory chips to which data can simultaneously be written in the event of a write access is dependent on the form of organization of the memory chips and a data width of the external access bus. In the case of a bus width of the external access bus of 72 bits and .times.8 form of organization, a read or write access is simultaneously effected to 9 memory chips of the memory module, which build a so-called rank, and eight data signals are simultaneously read out from the memory cells. Thus in the 4R. times.8 module configuration, 36 memory chips are distributed between 4 ranks. The memory chips are arranged in two rows on a top side of a module board and in two rows on an underside of the...