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Browse Prior Art Database

on-chip test structure

IP.com Disclosure Number: IPCOM000169987D
Original Publication Date: 2008-May-05
Included in the Prior Art Database: 2008-May-05
Document File: 4 page(s) / 38K

Publishing Venue

IBM

Abstract

Early yield test of critical circuit component such as storage element is very important for success of microprocessor/ASIC on cutting-edge semiconductor technology. The current known solution is to simpliy connect all the storage elements together seriesly by their scan chain pins. And then we can find out whether there is problem in these elements by scaning-in and scaning-out signal into this chain. The drawback is it can not identify which element fails. So engineers have to search for a manufacturing defect over a very big area, which is very time consuming and needs lots of efforts. The other method is to use additional scan chains to copy the defective scan chain’s contents, then scan out to check; each storage element requires additional MUX; the drawback is we need one MUX for each storage element and control logic to control MUX, which increases area, design effort and possible yield problem due to these extra gates and signal routings We invent an on-chip test structure and methodology for storage elements. The advantages are: 1) able to identify single and multiple failed elements from the scan chain 2) able to identify which part of storage element fails

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 56% of the total text.

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on-chip test structure

Scan Chain Diagnostics

Ming Yin, Thomas Ludwig

Disclosed is a system and method for diagnosing defect problem on scan chain of storage elements. This invention uses regular scan chain to serially connect storage elements by their scan in and scan out pins; the storage elements in the scan chain also connects its data pins to the data pins of its right-side storage elements in the same scan chain. This method uses regular scan chain during the normal scan mode; if there is any defective latch/register within scan chain, go to the parallel shift mode and then scan mode

The advantages of this method are:

Able to detect single defective storage element

 
Only need two MUX gates for one column of storage elements instead of one MUX gate per storage element

Signal routing from control logic to MUX gates also


Reduced area overhead for MUX gates, signal routing and control logic Reduced design effort due to much less MUX gates and signal routing Reduced yield problems due to MUX gates and signal routing

In Fig.1, this test structure has a single chain of storage elements including 2 columns. Every storage element is connected to its next 2 storage elements (top and bottom) by scan-in (si) and scan-out (so) pins. Every storage element is also connected to its next storage element (left or right) by data-in (di) and data-out (do) pins.

This test structure has 2 test modes. The first test mode is to shift scan-input data through all 2 columns. The scan-in data come into the first storage element, which is the top element of first column. Then through the scan chain it will go through 1st column, to 2nd column. In this way it can test all the elements in one time.

The second test mode is to split the original signal scan chain into 2 scan chains by controlling 4 MUX gates, and then parallel shift data between 2 storage elements by their data-in (di) and data-out (do) pins; then run the regular scan chain test mode to shift scan-data out from 2 scan chains; scan outputs can be examined to find out the defective storage element. The way to do parallel shift is to disable scan model and enable normal function mode for storage elements.

1

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Scan in1

Scan in2

si
di do so

si
di do so

si
di do so

si
di do so

1

si
di do so

si
di do so

2

si
di do so

si
di do so

Scan out1

Scan out2

Scan out

Fig.1 On-chip Scan Chain Structure

Here is one example shown in Fig.2.

Assume storage element "2" in scan-chain 2 is stuck at "1". Scan in1 is "0" and scan in2 is "0". Under test-mode 1(single scan chain), we'll get "00000000". Under test-mode 2(2 scan chains), we first scan in/out these 2 chains and get "0000" for scan chain1 and "1111" for scan chain2. Under test-mode2,...