Browse Prior Art Database

Efficient implementation of store with duplicate/swap of RISC registers, without increasing OpCode.

IP.com Disclosure Number: IPCOM000171093D
Publication Date: 2008-May-28
Document File: 2 page(s) / 76K

Publishing Venue

The IP.com Prior Art Database

Abstract

RISC processors may be found in abundance in modern System on a Chip (SoC) designs. The operational code (OpCode) efficiency has a profound effect on the performance of the RISC and SoC itself thus making such improvments a major goal for every RISC designer. Reducing or maintaining the OpCode size allows the SoC to keep smaller memory devices, a goal by itself. Accesses made by the RISC processor to it's data RAM makes a sizable portion of every RISC OpCode and improving it will allow the OpCode to be shorter and the RISC operation more efficient. Current RISC processors stores data required for immediate operations in general purpose registers before moving their content to a data RAM. The possible options are to store either one register or a pair of registers - while the first register (R1 for example) is always stored in the lower address of the data RAM and the second register (R2) is stored to the higher address of the data RAM. This limits the possibilities available to manipulate the registers. In addition it does not allow storage of the same register (duplication of register) to consecutive addresses (in the data RAM) in the same instruction, thus increasing the OpCode.

This text was extracted from a Microsoft Word document.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 53% of the total text.

Efficient implementation of store with
duplicate/swap of RISC registers, without
increasing OpCode.

 

I.     Abstract

RISC processors may be found in abundance in modern System on a Chip (SoC) designs. The operational code (OpCode) efficiency has a profound effect on the performance of the RISC and SoC itself thus making such improvments a major goal for every RISC designer. Reducing or maintaining the OpCode size allows the SoC to keep smaller memory devices, a goal by itself.

Accesses made by the RISC processor to it's data RAM makes a sizable portion of every RISC OpCode and improving it will allow the OpCode to be shorter and the RISC operation more efficient. Current RISC processors stores data required for immediate operations in general purpose registers before moving their content to a data RAM. The possible options are to store either one register or a pair of registers - while the first register (R1 for example) is always stored in the lower address of the data RAM and the second register (R2) is stored to the higher address of the data RAM. This limits the possibilities available to manipulate the registers. In addition it does not allow storage of the same register (duplication of register) to consecutive addresses (in the data RAM) in the same instruction, thus increasing the OpCode.

II.    Solution and Implemetation

The suggested solution offers to store of a pair of general purpose registers to a data RAM either by order (meaning {R1[0:31], R2[0:31]} or in a reverse order ({R2[0:31],R1[0:31]}) or duplicating one of the registers when storing ({R1[0:31],R1[0:31]} or R2[0:31],R2[0:31]). The...