Browse Prior Art Database

I/O optimization using hardware caching as part of the optimization algorithm

IP.com Disclosure Number: IPCOM000172860D
Original Publication Date: 2008-Jul-16
Included in the Prior Art Database: 2008-Jul-16
Document File: 1 page(s) / 24K

Publishing Venue

IBM

Abstract

A method for I/O optimization utilizing knowledge of hardware caching as part of the optimization algorithm

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 76% of the total text.

Page 1 of 1

I/O optimization using hardware caching as part of the optimization algorithm

Disclosed is a method for utilizing knowledge of hardware caching as part of the optimization algorithm.

Current disk access optimization methodology allows for reordering I/O accesses to minimize rotational delay and increase throughput. However, the current algorithms do not take advantage of caching that takes place within the hardware device. For example, the hardware may be placing data for a track or tracks in its cache and delaying the writing of the data to disk. Alternatively, data may already be in the cache and not need to be read from disk. If the operating system or device driver managing the I/O access to disk is not aware of the disk algorithm then the ordering of request may not provide for the best optimization. Because the cost of processors is becoming cheaper, the ability to use separate cores in the hardware to communicate with software is a reasonable extension for improving throughput. Caching within the hardware and support for communication between the hardware and software to improve throughput is expected to be an area for improved throughput. Separate interfaces or new support to guarantee that data will be written even on power failure or at least commands to force the flushing of specific data are assumed.

The invention adds an interface to the disk controller to return an indication that an I/O request is being plac...