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FF structure for setup failure recovery design with increased time for error propagation and combined SRPG support

IP.com Disclosure Number: IPCOM000174104D
Publication Date: 2008-Aug-26
Document File: 3 page(s) / 51K

Publishing Venue

The IP.com Prior Art Database

Abstract

During the last years, the required ratio of performance-to-power is continuously growing. To answer this challenge, inventing new power saving techniques and improving an existing ones are needed. The presented publication discusses in details an improvement of the power saving technique, where the 'error propagation' time is significantly increased vs. the currently published version.

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FF structure for setup failure recovery design with increased time for error propagation and combined SRPG support  

Abstract

During the last years, the required ratio of performance-to-power is continuously growing. To answer this challenge, inventing new power saving techniques and improving an existing ones are needed. The presented publication discusses in details an improvement of the power saving technique, where the 'error propagation' time is significantly increased vs. the currently published version.

Introduction

Supply voltage adjustment per frequency and process speed performance is one of the most aggressive power management techniques.

One of the main problems is defining margins, that are required to guarantee robust functionality. Intra-die variation, SI noise and some other statistical events, that can impact critical path delay, could require pretty high margins in supply voltage, while actually can cause setup violation in very rare cases.

Design, that is tolerant to setup failures, will allow to reduce supply voltage significantly and adjust it, depends on failures rate.

One of the most known references of such design methodologies is Razor.

One of the main problems in existing technologies is very small time for setup error propagation. Sample of “correct” signal is done by special signal or by clock negedge. Next...