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Flow Control Based DMA Architecture

IP.com Disclosure Number: IPCOM000174431D
Original Publication Date: 2008-Sep-24
Included in the Prior Art Database: 2008-Sep-24
Document File: 4 page(s) / 467K

Publishing Venue

Siemens

Related People

Juergen Carstens: CONTACT

Abstract

A network processor system comprises in general a central network processor, a RAM (Random Access Memory) memory subsystem and a plurality of peripheral subsystems which are connected in common to a system bus. The system bus timing is divided into a plurality of fixed time slots including a CPU (Central Processor Unit) bus cycle and a plurality of DMA (Direct Memory Access) bus cycles. The central processor subsystem communicates with the memory subsystem during CPU bus cycles and the peripheral subsystems communicate with the memory subsystem on DMA bus cycles. DMA controllers are used extensively in SOCs (System-on-a-chip) for bulk transfer of data from memory to peripherals. DMA cycles are handled by a DMA system and significantly reduce the reliance on the network processor when transferring data between high-speed I/O (Input/Output) modules and SDRAM (Synchronous Dynamic RAM) memory. DMA systems include either a central DMA controller or a DMA controller within each of the high-speed I/O modules which connects directly to the Transmit and Receive FIFOs within the module; a dedicated DMA port on the SDRAM controller; and a dedicated high-speed 32-bit DMA bus or shared system bus, linking the DMA controllers to the SDRAM controller. DMA transfers between the I/O module, FIFOs (First-In First-Out), and the SDRAM take place in parallel with other network processor operation. Thereby, CPU access is required only at the start and end of the packet cell. A single DMA transfer across the bus (e.g. a burst) is between one and 16 words. The 16 word limit prevents any device from occupying the DMA bus. If larger DMA data transfers are required, they are automatically split into multiple 16-word bursts. Write performance is enhanced by buffering in the SDRAM controller. However, data transmission through the peripheral depends on its flow control state and internal FIFO availability. For example, a DMA transaction on a paused peripheral will hold-on the shared bus for the paused period, preventing access by other peripherals down the queue. These paused-transaction scenarios result in wasted bandwidth and slow down the overall system performance.

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Flow Control Based DMA Architecture

Idea: Ashish Ashputre, IN-Bangalore

A network processor system comprises in general a central network processor, a RAM (Random Access Memory) memory subsystem and a plurality of peripheral subsystems which are connected in common to a system bus. The system bus timing is divided into a plurality of fixed time slots including a CPU (Central Processor Unit) bus cycle and a plurality of DMA (Direct Memory Access) bus cycles. The central processor subsystem communicates with the memory subsystem during CPU bus cycles and the peripheral subsystems communicate with the memory subsystem on DMA bus cycles.

DMA controllers are used extensively in SOCs (System-on-a-chip) for bulk transfer of data from memory to peripherals. DMA cycles are handled by a DMA system and significantly reduce the reliance on the network processor when transferring data between high-speed I/O (Input/Output) modules and SDRAM (Synchronous Dynamic RAM) memory. DMA systems include either a central DMA controller or a DMA controller within each of the high-speed I/O modules which connects directly to the Transmit and Receive FIFOs within the module; a dedicated DMA port on the SDRAM controller; and a dedicated high-speed 32-bit DMA bus or shared system bus, linking the DMA controllers to the SDRAM controller. DMA transfers between the I/O module, FIFOs (First-In First-Out), and the SDRAM take place in parallel with other network processor operation. Thereby, CPU access
is required only at the start and end of the packet cell. A single DMA transfer across the bus (e.g. a burst) is between one and 16 words. The 16 word limit prevents any device from occupying the DMA bus. If larger DMA data transfers are required, they are automatically split into multiple 16-word bursts. Write performance is enhanced by buffering in the SDRAM controller. However, data transmission through the peripheral depends on its flow control state and internal FIFO availability. For example, a DMA transaction on a paused peripheral will hold-on the shared bus for the paused period, preventing access by other peripherals down the queue. These paused-transaction scenarios result in wasted bandwidth and slow down the overall system performance.

At present, there are two approaches to solve the problem described above. In the first approach, the CPU polls frequently to find the FIFO availability of the transmit peripheral and then to program accordingly the data length in the DMA descriptors. The disadvantage of this solution is that frequent CPU polling slows down the system performance. Furthermore, CPU has to write multiple DMA descriptors with data length according to available FIFO size. Thus, a bulk transfer which could otherwise be a single transaction gets divided into multiple transactions. Overall...