Slew Rate Control Using Multi-Leg Predriver
Publication Date: 2008-Sep-17
The IP.com Prior Art Database
AbstractFast edge rates are a major contributing factor to high SSO. By reducing signal edge rates at the pad, SSO is reduced for two reasons:
Fast edge rates are a major contributing factor to high SSO. By reducing signal edge rates at the pad, SSO is reduced for two reasons:
1. Slower edge rates reduce the noise due to mutual coupling caused by adjacent aggressors.
2. Slower edge rates reduce the peak current required per transition, which help the overall signal integrity of the chip.
Because general purpose IOs, which support IO standards with VCCN ranges of 1.2V to 3.3V, they require pre-drivers to drive their output drivers for any voltage in the range of 1.2V to 3.3V. Since the same devices that operate at 1.2V are operating at 3.3V, the pre-driver output tends to have much faster edge rates for 3.3V standards. These faster edge rates increase SSO as explained before. Please see Figure 1 for a block diagram of a traditional output buffer, which is comprised of a pre-driver and an output driver.
Figure 1: Block Diagram of an output buffer
This invention allows for the control of the edge rates at the output of the pre-drivers. By controlling how fast you turn on the output driver, the circuit indirectly controls the edge rates at the pad. As shown in Figure 2, the pull up pre-driver’s Nmos is broken down into three legs each separately controlled by an option bit.
Figure 2: Block Diagram of pull up pre-driver
Note that for the pull-up p...