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Scan Test Power Reduction Using Gated Clock for Multiple San Segments in Scan Chains of Improved Multiple-input Illinois Scan Architecture

IP.com Disclosure Number: IPCOM000174796D
Publication Date: 2008-Sep-24
Document File: 7 page(s) / 102K

Publishing Venue

The IP.com Prior Art Database

Abstract

With the increasing number of transistors in an IC chip, testing is becoming more and more complex. How to generate efficient pattern seeds without adding test cost and reducing the test power dissipation as much as possible is a challenge faced by design-for-test engineers. Herein, we adopt gated clocks to keep unused scan cells no change in scan chains. The test coverage is the same with the method of adding another multiplexer on traditional scan cells; at the same time, using gated clocks can also switch off the toggling of the don't-care bits on scan cells. Based on this methodology, the improved scan architecture of Illinois Scan Architecture (ISA) can reduce the redundant pattern seeds and reduce the power consumption in scan test simultaneously. Key Word: ISA, scan segment, gated clock, ATPG, pattern seeds

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Title:

Scan Test Power Reduction Using Gated Clock for Multiple San Segments in Scan Chains of Improved Multiple-input

Illinois

Scan Architecture

Abstract

With the increasing number of transistors in an IC chip, testing is becoming more and more complex.  How to generate efficient pattern seeds without adding test cost and reducing the test power dissipation as much as possible is a challenge faced by design-for-test engineers.  Herein, we adopt gated clocks to keep unused scan cells no change in scan chains.  The test coverage is the same with the method of adding another multiplexer on traditional scan cells; at the same time, using gated clocks can also switch off the toggling of the don’t-care bits on scan cells.  Based on this methodology, the improved scan architecture of Illinois Scan Architecture (ISA) can reduce the redundant pattern seeds and reduce the power consumption in scan test simultaneously.

Key Word: ISA, scan segment, gated clock, ATPG, pattern seeds

Body

With scan-based design widely used in integrated circuit and the complexity of circuits continuing to increase, test time and test pattern volume that meet high fault coverage increase substantially. How to design a scan architecture that can make both the test time even shorter and test pattern more cost-effective is a challenge for design-for-test engineer. The fact that a majority of the ATPG bits (95-99%, see T. Hiraide, K. O. Boateng, H. Konishi, K. Itaya, M. Emori and H. Yamanaka, "BIST-Aided Scan Test--A New Method for Test Cost Reduction," VLSI Test Symposium (VTS'03), pp. 359-364, April 2003) are don't-care bits makes ISA an attractive solution for pattern volume and test time.  ISA is one of the scan architectures used for multiple scan chains by sharing one scan input to decrease scan input channels.  For the independent sub-blocks with balanced scan chains, the advantage of using Illinois scan can keep all the sub-blocks’ original faults coverage and is also likely to reduce test pattern volume as much as ATPG (Auto Test Pattern Generation) tool can.  However, if the sub-blocks are not independent, the property of detecting all faults is not guaranteed.  Therefore, the serial mode for each sub-blocks scan pattern generation is used to improve the test faults coverage at the cost of using the larger test pattern volume.

For the general application of design-for-test based on

Illinois

scan,

Illinois

scan architecture has two modes of operations, namely: a) broadcast mode; b) serial mode. Using only one scan channel to drive all scan chains in ISA is not feasible with the increasing number of transistors on circuit design in broadcast mode.  At the same time, running scan test in serial mode is no advantage to improve test pattern efficiency without adding test pattern volume.  Therefore, a multiple-input ISA, discu...