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Novel Methodology for Qualification and Timing Closure of Multiple EDA Tools

IP.com Disclosure Number: IPCOM000176535D
Original Publication Date: 2008-Nov-14
Included in the Prior Art Database: 2008-Nov-14
Document File: 4 page(s) / 34K

Publishing Venue

IBM

Abstract

System of methodology steps to ensure close timing closure among various global routers.

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This is the abbreviated version, containing approximately 44% of the total text.

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Novel Methodology for Qualification and Timing Closure of Multiple EDA Tools

Novel Methodology for Qualification and Timing Closure of Multiple EDA ToolsNovel Methodology for Qualification and Timing Closure of Multiple EDA Tools

Disclosed is a system to qualify global routers of various EDA tools. One of the EDA system tool can be used by a customer and the other can be used by an ASIC foundry. The goal is to have a good timing correlation between two EDA tools when the design is gone through placement and global routing.

The system's novelty is in its comprehensive approach to analyze all the end point timing paths regardless of slack value, analyze all the paths using mixture of slack and arrival times and heusristics for correlation of layer assignments for global routers.

The approach is comprised of several steps explained below.

The first step of our methodology is to insure that input to the EDA tools are the same. EDA tools use different input format and one needs to make sure the tools interpret the data the same way. One key input to the qualification effort is to insure the same resistance and capacitance values are seen by the tools.

The second step is to make sure that both tools have the same area constraints for placement and routing by making sure both tools do the same power routing and FILLER cell insertion. This process is for most part a manual check of a design in both systems. Programs can be written to automatically verify the constraints as well.

The third step is to run zero wire load timing (ZWL) on the two EDA tools and identify any discrepancies. Zero wire load timing assumes that there is no delay contribution due to wire delay. To assist for this analysis, programs are written to query all the arrival time and slacks of target sample designs endpoints. This is an important departure from traditional negative slack timing comparison only. There are situations that timing libraries may have different behaviors in interrelation in reporting of slack among EDA tools but have similar arrival times. We have seen situations whereas different slack is reported for a path ending to a latch (i.e. half cycle vs full cycle) but they have similar arrival times. Using arrival times one can identify discrepancies of all the end points irrespective of critically of timing slack. Typically such discrepancies should be minimal to have a good correlation at the global route level. In this step discrepancies can generally be identified due to: a) timing tool differences b) different interpretation of timing rules c) timing assertion misinterpretation d) out of range slew and cap e) different timing option among the tools.

One can also analyze timing correlation by a hybrid approach as well. Library cells (mostly latches) that have different timing behavior (EDA tool A and B) are identified. Timing and correlation of paths ending at these cells will be based on arrival times. All...